Talk:6264 static RAM: Difference between revisions
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Gnd D3<br> | Gnd D3<br> | ||
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These would need to be edited to match formatting of the existing Wiki article. | LY6220488 TSOP-package SRAM (32 pins, 1-16, 32-17)<br> | ||
A4 A5<br> | |||
A3 A6<br> | |||
A2 A7<br> | |||
A1 !OE<br> | |||
A0 CS2<br> | |||
!CS A8<br> | |||
NC NC<br> | |||
NC NC<br> | |||
D0 D7<br> | |||
D1 D6<br> | |||
+5V Gnd<br> | |||
Gnd +5V<br> | |||
D2 D5<br> | |||
D3 D4<br> | |||
NC NC<br> | |||
A20 NC<br> | |||
!WE A9<br> | |||
A19 A10<br> | |||
A18 A11<br> | |||
A17 A12<br> | |||
A16 A13<br> | |||
A15 A14<br> | |||
<br> | |||
These would need to be edited to match formatting of the existing Wiki article.<br> | |||
Revision as of 17:00, 30 August 2014
More pinouts for different sizes of 62* SRAM's
Some extra pinouts for SRAMs:
62256 is identical except for the !CS2 input and NC becoming address lines. This is to make address expansion of a board design almost trivial using inverters as half of an address decoder (other half is !CS input).
CY62256 SRAM (28 pins, 1-14,28-15) Note that the Ax and Dx line order doesn't really matter.
A5 +5V
A6 !WE
A7 A4
A8 A3
A9 A2
A10 A1
A11 !OE
A12 A0
A13 !CS
A14 D7
D0 D6
D1 D5
D2 D4
Gnd D3
62512 SRAM (32 pins, 1-16, 32-17)
A18 +5V
A16 A15
A14 A17
A12 /WE
A7 A13
A6 A8
A5 A9
A4 A11
A3 /OE
A2 A10
A1 /CS
A0 D7
D0 D6
D1 D5
D2 D4
Gnd D3
621024 SRAM (32 pins, 1-16, 32-17)
NC +5V
A16 A15
A14 CS2
A12 /WE
A7 A13
A6 A8
A5 A9
A4 A11
A3 /OE
A2 A10
A1 /CS1
A0 D7
D0 D6
D1 D5
D2 D4
Gnd D3
LY6220488 TSOP-package SRAM (32 pins, 1-16, 32-17)
A4 A5
A3 A6
A2 A7
A1 !OE
A0 CS2
!CS A8
NC NC
NC NC
D0 D7
D1 D6
+5V Gnd
Gnd +5V
D2 D5
D3 D4
NC NC
A20 NC
!WE A9
A19 A10
A18 A11
A17 A12
A16 A13
A15 A14
These would need to be edited to match formatting of the existing Wiki article.
