VRC3

The Konami VRC3 is an ASIC mapper.

Overview

• PRG ROM size: Up to 128 KB
• PRG ROM bank size: 16 KB at $8000
• PRG RAM: 8 KB at $6000
• CHR: 8 KB RAM, not swappable
• Nametable mirroring: Solder pads select vertical or horizontal mirroring
• Subject to bus conflicts: No

Registers

PRG Select ($F000-$FFFF)

7  bit  0
---------
.... PPPP
     ||||
     ++++- Select 16 KB PRG ROM at $8000

IRQ Latch 0 ($8000-$8FFF)

7  bit  0
---------
.... LLLL
     ||||
     ++++- Bits 0-3 of IRQ latch.

IRQ Latch 1 ($9000-$9FFF)

7  bit  0
---------
.... LLLL
     ||||
     ++++- Bits 4-7 of IRQ latch.

IRQ Latch 2 ($A000-$AFFF)

7  bit  0
---------
.... LLLL
     ||||
     ++++- Bits 8-11 of IRQ latch.

IRQ Latch 3 ($B000-$BFFF)

7  bit  0
---------
.... LLLL
     ||||
     ++++- Bits 12-15 of IRQ latch.

IRQ Control ($C000-$CFFF)

7  bit  0
---------
.... .MEA
      |||
      ||+- IRQ Enable on Acknowledgement (see $D000)
      |+-- IRQ Enable (1=enabled)
      +--- IRQ Mode (1=8-bit counter, 0=16-bit counter)

Any write to this register will acknowledge the pending IRQ. If this register is written to with the 'E' bit set, the 16-bit IRQ counter is reloaded with the 16-bit Latch value (set by writes to $8000-$BFFF).

IRQ Acknowledge ($D000-$DFFF)

7  bit  0
---------
.... ....

Any write to this register will acknowledge the pending IRQ. In addition, the 'A' control bit moves to the 'E' control bit, enabling or disabling IRQs. Writes to this register do not affect the current state of the IRQ counter.

IRQ Counter Operation

IRQs on this mapper are generated through a 16-bit counter, which is incremented each CPU cycle (if enabled). When it overflows from $FFFF, an IRQ is generated, and the counter is reloaded with the 16-bit latch value.

When the IRQ mode bit ('M') is set, the upper 8 bits of the counter are ignored and IRQs are generated when the lower 8 bits overflow from $FF.

When IRQs are disabled ('E' control bit clear), the IRQ counter does not increment.