CPU: Difference between revisions
From NESdev Wiki
Jump to navigationJump to search
(Add note about every cycle being either read or write. Not sure if this is the best spot...) |
(Add link to the 2A03 technical reference document) |
||
| Line 32: | Line 32: | ||
* Every cycle on 6502 is either a read or a write cycle. | * Every cycle on 6502 is either a read or a write cycle. | ||
* A printer friendly version covering all section is available [[CPU ALL|here]]. | * A printer friendly version covering all section is available [[CPU ALL|here]]. | ||
=== See also === | |||
* [http://nesdev.org/2A03%20technical%20reference.txt 2A03 technical reference] by Brad Taylor. (Pretty old at this point; information on the wiki might be more up-to-date.) | |||
Revision as of 05:56, 14 April 2013
The NES CPU core is based on the 6502 processor and runs at approximately 1.79 MHz (1.66 MHz in a PAL NES). It is made by Ricoh and lacks the MOS6502's decimal mode. In the NTSC NES, the RP2A03 chip contains the CPU and APU; in the PAL NES, the CPU and APU are contained within the RP2A07 chip.
Sections
- CPU instructions
- CPU addressing modes
- CPU memory map
- CPU power-up state
- CPU status flag behavior
- CPU interrupt quirks
- Unofficial opcodes
- CPU pin-out and signals, and other hardware pin-outs
CPU signals and frequencies
The CPU generates its clock signal by dividing the master clock signal.
| Rate | NTSC NES/Famicom | PAL NES | PAL Famiclone |
|---|---|---|---|
| Color subcarrier frequency fsc (exact) | 39375000/11 Hz | 4433618.75 Hz | 4433618.75 Hz |
| Color subcarrier frequency fsc (approx.) | 3.579545 MHz | 4.433619 MHz | 4.433619 MHz |
| Master clock frequency 6fsc | 21.477272 MHz | 26.601712 MHz | 26.601712 MHz |
| Clock divisor d | 12 | 16 | 15 |
| CPU clock frequency 6fsc/d | 1.789773 MHz | 1.662607 MHz | 1.773448 MHz |
Notes
- Kevtris has confirmed that all illegal 6502 opcodes execute identically on the 2A03/2A07. He has even went as far as to integrate them into the CopyNES BIOS.
- Every cycle on 6502 is either a read or a write cycle.
- A printer friendly version covering all section is available here.
See also
- 2A03 technical reference by Brad Taylor. (Pretty old at this point; information on the wiki might be more up-to-date.)
