Sunsoft FME-7: Difference between revisions
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== Registers == | == Registers == | ||
Configuration of the FME-7 is accomplished by first writing the command number to the Command Register, then writing the command's parameter byte to the Parameter Register. | Configuration of the FME-7 is accomplished by first writing the command number to the Command Register, then writing the command's parameter byte to the Parameter Register. | ||
There are 16 commands: | |||
* '''$0-7''' control CHR banking | |||
* '''$8-B''' control PRG banking | |||
* '''$C''' controls nametable mirroring | |||
* '''$D-F''' controls IRQ | |||
=== Command Register ($8000-$9FFF) === | === Command Register ($8000-$9FFF) === |
Revision as of 02:27, 2 March 2015
The Sunsoft FME-7 represents two mapper ICs which work identically, except that one contains extra sound hardware. The FME-7 is the base memory mapper with no additional sound hardware. The Sunsoft 5B is an FME-7 with the addition of extra sound hardware. Both the Sunsoft 5B and FME-7 exist as a 44 pin TQFP. It is emulated as iNES Mapper 069.
In Europe, boards using the FME-7 were labeled as JSROM and JLROM. The FME-7 mapper was used in only one game released in the US, Batman: Return of the Joker.
Many Japanese releases by Sunsoft used the FME-7: Gimmick!, Hebereke, Gremlins 2 (but not in the US version), Barcode World, and others.
Overview
- Manufacturer: Sunsoft
- PRG ROM Size: Up to 256 KiB on 5B; Up to 512 KiB on FME-7; at least 256 KiB on 5A but unknown.
- PRG ROM Bank Size: 8 KiB
- PRG RAM: Up to 8 KiB, and possibly more
- CHR capacity: 256 KiB
- CHR Bank Size: 1 KiB
- Nametable mirroring: Controlled by Mapper: H, V, 1scA, 1scB
- Subject to bus conflicts: No
Banks
- CPU $6000-$7FFF: 8 KB Bankable PRG ROM or PRG RAM
- CPU $8000-$9FFF: 8 KB Bankable PRG ROM
- CPU $A000-$BFFF: 8 KB Bankable PRG ROM
- CPU $C000-$DFFF: 8 KB Bankable PRG ROM
- CPU $E000-$FFFF: 8 KB PRG ROM, fixed to the last bank of ROM
- PPU $0000-$03FF: 1 KB Bankable CHR ROM
- PPU $0400-$07FF: 1 KB Bankable CHR ROM
- PPU $0800-$0BFF: 1 KB Bankable CHR ROM
- PPU $0C00-$0FFF: 1 KB Bankable CHR ROM
- PPU $1000-$13FF: 1 KB Bankable CHR ROM
- PPU $1400-$17FF: 1 KB Bankable CHR ROM
- PPU $1800-$1BFF: 1 KB Bankable CHR ROM
- PPU $1C00-$1FFF: 1 KB Bankable CHR ROM
Registers
Configuration of the FME-7 is accomplished by first writing the command number to the Command Register, then writing the command's parameter byte to the Parameter Register.
There are 16 commands:
- $0-7 control CHR banking
- $8-B control PRG banking
- $C controls nametable mirroring
- $D-F controls IRQ
Command Register ($8000-$9FFF)
7 bit 0 ---- ---- .... CCCC |||| ++++- The command number to invoke when writing to the Parameter Register
Parameter Register ($A000-$BFFF)
7 bit 0 ---- ---- PPPP PPPP |||| |||| ++++-++++- The parameter to use for this command. Writing to this register invokes the command in the Command Register.
Commands
In order to invoke a command first write the command's number to the Command Register, then the desired parameter to the Parameter Register.
CHR Bank 0 ($0)
7 bit 0 ---- ---- BBBB BBBB |||| |||| ++++-++++- The bank number to select at PPU $0000 - $03FF
CHR Bank 1 ($1)
7 bit 0 ---- ---- BBBB BBBB |||| |||| ++++-++++- The bank number to select at PPU $0400 - $07FF
CHR Bank 2 ($2)
7 bit 0 ---- ---- BBBB BBBB |||| |||| ++++-++++- The bank number to select at PPU $0800 - $0BFF
CHR Bank 3 ($3)
7 bit 0 ---- ---- BBBB BBBB |||| |||| ++++-++++- The bank number to select at PPU $0C00 - $0FFF
CHR Bank 4 ($4)
7 bit 0 ---- ---- BBBB BBBB |||| |||| ++++-++++- The bank number to select at PPU $1000 - $13FF
CHR Bank 5 ($5)
7 bit 0 ---- ---- BBBB BBBB |||| |||| ++++-++++- The bank number to select at PPU $1400 - $17FF
CHR Bank 6 ($6)
7 bit 0 ---- ---- BBBB BBBB |||| |||| ++++-++++- The bank number to select at PPU $1800 - $1BFF
CHR Bank 7 ($7)
7 bit 0 ---- ---- BBBB BBBB |||| |||| ++++-++++- The bank number to select at PPU $1C00 - $1FFF
PRG Bank 0 ($8)
7 bit 0 ---- ---- ER.B BBBB || | |||| || +-++++- The bank number to select at CPU $6000 - $7FFF |+------- RAM / ROM Select Bit | 0 = PRG ROM | 1 = PRG RAM +-------- RAM Enable Bit (6264 +CE line) 0 = PRG RAM Disabled 1 = PRG RAM Enabled
It is very likely that a cartridge could be modified to support banking up to 256 KiB of PRG-RAM here. However, no game was ever released with more than 8KiB and this is currently untested. At least one version of the FME-7 mapper for the PowerPak supports 32 KiB.
Values $40-$7F produce open bus: the RAM / ROM Select Bit is 1 (RAM selected), but the RAM Enable Bit is 0 (disabled). This is a limited form of WRAM write protection on power-up.
There is a tentative report that not all games honor some or any of the bits in this register. Corroboration is needed before any action is taken.
PRG Bank 1 ($9)
7 bit 0 ---- ---- ...B BBBB | |||| +-++++- The bank number to select at CPU $8000 - $9FFF
PRG Bank 2 ($A)
7 bit 0 ---- ---- ...B BBBB | |||| +-++++- The bank number to select at CPU $A000 - $BFFF
PRG Bank 3 ($B)
7 bit 0 ---- ---- ...B BBBB | |||| +-++++- The bank number to select at CPU $C000 - $DFFF
Name Table Mirroring ($C)
These values are the same as MMC1 mirroring modes with the MSB inverted.
7 bit 0 ---- ---- .... ..MM || ++- Mirroring Mode 0 = Vertical 1 = Horizontal 2 = One Screen Mirroring from $2000 ("1ScA") 3 = One Screen Mirroring from $2400 ("1ScB")
IRQ Control ($D)
7 bit 0 ---- ---- C... ...T | | | +- IRQ Enable | 0 = Do not generate IRQs | 1 = Do generate IRQs +-------- IRQ Counter Enable 0 = Disable Counter Decrement 1 = Enable Counter Decrement
All writes to this register acknowledge an active IRQ.[1] It is not yet known what will happen if this register is written to at the same time as an IRQ would have been generated.
IRQ Counter Low Byte ($E)
7 bit 0 ---- ---- LLLL LLLL |||| |||| ++++-++++- The low eight bits of the IRQ counter. Note that setting this register directly sets the lower eight bits of the counter.
IRQ Counter High Byte ($F)
7 bit 0 ---- ---- HHHH HHHH |||| |||| ++++-++++- The high eight bits of the IRQ counter. Note that setting this register directly sets the upper eight bits of the counter.
IRQ Operation
The IRQ feature of FME-7 is a CPU cycle counting IRQ generator. When enabled the 16-bit IRQ counter is decremented once per CPU cycle. When the IRQ counter is decremented from $0000 to $FFFF an IRQ is generated. The IRQ line is held low until it is acknowledged.
How to Use the IRQ Generator
- Set the counter to the desired number of cycles minus one.
- Enable the IRQ generator by turning on both the IRQ Enable and IRQ Counter Enable flags of the IRQ Control command.
- Within the IRQ handler, write to the IRQ Control command to acknowledge the IRQ.
- Optional: Go back to Step 1 for the next IRQ.
Disch's Notes
Here are Disch's (lightly edited) notes: ======================== = Mapper 069 = ======================== aka -------------------------- Sunsoft FME-7 Sunsoft 5B Example Games: -------------------------- Gimmick! Batman: Return of the Joker Hebereke Gremlins 2 (J) Notes: -------------------------- This mapper is FME-7 and compatible. Sunsoft 5B operates the same as FME-7, only it has additional sound hardware. For a long time, it was thought Gimmick! uses FME-7, so the expansion sound is labeled as FME-7 in various places -- however -- technically FME-7 has no extra sound. Gimmick! is the only known game to use the extra sound found on Sunsoft 5B Registers: -------------------------- Range,Mask: $8000-FFFF, $E000 $8000: [.... AAAA] Address for use with $A000 $A000: [DDDD DDDD] Data port R:0-7 -> CHR Regs R:8-B -> PRG Regs R:C -> Mirroring R=D-F -> IRQ Control $C000: [.... AAAA] Address for use with $E000 (sound) $E000: [DDDD DDDD] Data port (sound -- see sound section) PRG Setup: --------------------------- R:8 controls $6000-7FFF. It can map in PRG-RAM, PRG-ROM, or leave it unmapped (open bus), depending on the mode it sets: R:8: [ERPP PPPP] E = Enable RAM (0=disabled, 1=enabled) R = RAM/ROM select (0=ROM, 1=RAM) P = PRG page if E=0 and R=1, RAM is selected, but it's disabled, resulting in open bus. In case it's still unclear: R=0: ROM @ $6000-7FFF R=1, E=0: Open Bus @ $6000-7FFF R=1, E=1: RAM @ $6000-7FFF R:9 - R:B appear to be a full 8 bits: [PPPP PPPP], and select only ROM. $6000 $8000 $A000 $C000 $E000 +-------+-------+-------+-------+-------+ | R:8 | R:9 | R:A | R:B | { -1} | +-------+-------+-------+-------+-------+ No games seem to use more than 8k PRG-RAM, so I'm unsure whether or not it's swappable when selected. I don't see why it wouldn't be. CHR Setup: --------------------------- $0000 $0400 $0800 $0C00 $1000 $1400 $1800 $1C00 +-------+-------+-------+-------+-------+-------+-------+-------+ | R:0 | R:1 | R:2 | R:3 | R:4 | R:5 | R:6 | R:7 | +-------+-------+-------+-------+-------+-------+-------+-------+ Mirroring: --------------------------- R:C: [.... ..MM] %00 = Vert %01 = Horz %10 = 1ScA %11 = 1ScB IRQs: --------------------------- This mapper has a 16-bit IRQ counter which decrements every CPU cycle. When it wraps from $0000->FFFF, an IRQ is tripped. reg R:E sets the low 8 bits of the counter reg R:F sets the high 8 bits Note the regs change the actual counter -- not a reload value. reg R:D is the IRQ control: [C... ...T] C = Enable countdown (0=disabled, 1=enabled) T = Enable IRQ triggering (0=disabled, 1=enabled) In order for IRQs to work as expected, both bits must be set. If either bit is cleared, an IRQ won't occur: C=0, T=1: IRQs are enabled, but the counter will never decrement C=1, T=0: Counter decrements, but IRQs are disabled Acknowledging IRQs can only be done by writing reg R:D
- ↑ Test performed in 2015 by Oliveira using IRQ acknowledge test ROM on NESdev BBS