PPU scrolling

Scrolling is the movement of the displayed portion of the map. Games scroll to show an area much larger than the 256x240 pixel screen. For example, areas in Super Mario Bros. may be up to 24 screens wide. The NES's first major improvement over its immediate predecessors (ColecoVision and Sega Mark 1) was pixel-level scrolling of playfields.

The common case

Ordinarily, a program writes to two PPU registers to set the scroll position near the end of vertical blanking, after it has made any updates to VRAM:

1. Find the X and Y coordinates of the upper left corner of the visible area (the part seen by the "camera")
2. Write the X coordinate to PPUSCROLL ($2005)
3. Write the Y coordinate to PPUSCROLL
4. Write the starting page (high order bit of X and Y) to bits 0 and 1 of PPUCTRL ($2000)

By itself, this allows moving the camera within a usually two-screen area (see Mirroring), with horizontal and vertical wraparound if the camera goes out of bounds.

To scroll over a larger area than the two screens that are already in VRAM, you figure out what columns or rows of the nametable are just coming into view, and you write that to VRAM before you set the scroll, as seen in the animation below. The area that needs rewritten at any given time is sometimes called the "seam" of the scroll.

What the registers do

Most uses of scrolling need not use any other registers. Raster effects such as split-screen scrolling, status bars, and 3D effects, on the other hand, need a more thorough understanding of the underlying mechanism.

Writing to PPUSCROLL ($2005) and PPUADDR ($2006) affects the same internal PPU registers, but in different ways. The same 15-bit VRAM address value is used both for the user to access the VRAM via PPUDATA ($2007) and for the PPU to make its own internal accesses to fetch name and attribute table data. There's also a 15-bit latch from which the VRAM address register is reloaded at various times. By convention, the VRAM address is often referred to as Loopy_V, and the latch as Loopy_T, since "V" and "T" were the mnemonics used by Loopy in his original document. In addition to the VRAM address and its corresponding latch, a fine X-scroll value {Loopy_X) is also utilized. This takes effect immediately, and controls which bit from the PPU's internal pixel shift registers will be selected.

Both PPUSCROLL and PPUADDR are designed to take two consecutive writes. Both registers share the same internal flip-flop for this purpose: the PPU treats it as a first write when it is false and as a second write when it is true. It toggles on any write to PPUSCROLL or PPUADDR and is set to false on reads from PPUSTATUS ($2002).

Writes to PPUSCROLL

The first write to PPUSCROLL controls the horizontal scroll offset. This is done by copying the lower three bits of the value written (pixel within tile) into Loopy_X, and the upper five bits (distance from left in tiles) into D4-D0 of Loopy_T. The coarse horizontal scroll offset will take effect when the next scanline is rendered, while the fine horizontal scroll offset in Loopy_X takes effect immediately.

The second write to PPUSCROLL controls the vertical scroll offset. The lower three bits of the value written (scanline within tile) are copied to D14-D12 of Loopy_T, and the upper five bits (distance from top in tiles) are copied to D9-D5 of Loopy_T. Since these bits are not reloaded into Loopy_V before rendering a scanline, they won't take effect until the next frame.

Writes to PPUADDR

The first write to PPUADDR sets the high address byte. Since the PPU's external address bus is only 14 bits in width, the top two bits of the value written are ignored. D14 of Loopy_T is cleared, while D13-D8 are loaded with the lower six bits of the value written.

The second PPUADDR write is copied in its entirety to D7-D0 of Loopy_T. More importantly, Loopy_T is then copied into Loopy_V. Games that perform scroll splits or extend vertical blanking use writes to PPUADDR instead of PPUSCROLL to handle scrolling at the split, since it is the only way to change the vertical scroll offsets during mid-frame rendering.

To perform such a split, games will perform a four-write sequence to PPUSCROLL and PPUADDR. It sets some bits more than once; only the last write to any given bit counts. When you count only those bits that don't get overwritten by a later write, the sequence looks like this:[1]

2006/1 ---- NN-- (nametable select)
2005/2 VV-- -vvv (upper two bits of coarse V scroll, all bits of fine V scroll)
2005/1 ---- -hhh (fine horizontal scrolling) (takes effect immediately)
2006/2 VVVH HHHH (lower three bits of coarse V scroll, all bits of coarse H scroll)

This forum post gives example code.

Timing

For the above code (writes to $2006, $2005, $2005, $2006):

• The first two writes only affect Loopy_T, so they can happen at any time.
• The third write (setting fine X) should happen at dot 256 or later. Since writes take 4 CPU cycles (12 PPU dots) to finish, the store to $2005 instruction should begin at dot 244 or later.
• The fourth write should happen before dot 304. The store to $2006 instruction should begin before dot 292.

Writes to PPUCTRL

Writing to PPUCTRL ($2000) also affects the VRAM address latch. The lower two bits of the value written (used for nametable selection) are copied to D11-D10 of Loopy_T.

Use of Loopy_V during rendering

At the beginning of each frame, the contents of Loopy_T are copied into Loopy_V, as long as background or sprites are enabled. This takes place on PPU cycle 304 of the pre-render scanline [2]. Also, at PPU cycle 257 after each scanline is rendered (assuming sprites or background are enabled), the PPU copies the six bits of Loopy_T that control horizontal scroll position (D10 and D4-D0) into Loopy_V, since they were altered in Loopy_V during scanline rendering.

References

• The skinny on NES scrolling by loopy