Namco 163 audio

The Namco 163 offers up to 8 additional sound channels that play wavetable samples while the 175 and 340 do not. Each waveform can be of a configurable length, and each channel has linear volume control. It has $80 bytes of sound RAM shared by channel registers and wavetable samples; at least $40 bytes are dedicated to samples, with more available if not all channels are used.

Like the Ensoniq DOC in the Apple IIGS, the chip is unable to clock every channel at once, so it cycles though channels, updating one every 15 CPU cycles. Because of this, the chip allows the game to configure the number of enabled channels. When fewer channels are enabled, the channels are clocked more often, allowing for higher tones with longer, more detailed waveforms. When more channels are enabled, clocking slows down since each channel has to wait its turn, resulting in lower tones and a high-pitched whining noise at the switching frequency. Most N163 games used only 4 channels.

Registers

Sound Enable ($E000-E7FF)

7  bit  0
---- ----
.SPP PPPP
 ||| ||||
 |++-++++- Select 8KB page of PRG-ROM at $8000
 +-------- Disables sound if set.

Sound is enabled on the N163 by writing a clear bit 6 to this register (0 is sufficient).

Address Port ($F800-$FFFF)

7  bit  0   (write only)
---- ----
IAAA AAAA
|||| ||||
|+++-++++- Address
+--------- Auto-increment

Writing to this register sets the internal address. If the 'I' bit is set, the address will increment on writes and reads to the Data Port ($4800), wrapping $7F->$00 (address is 7 bits wide)

Data Port ($4800-$4FFF)

7  bit  0   (read / write)
---- ----
DDDD DDDD
|||| ||||
++++-++++- Data

This Port accesses the N163's internal $80 bytes of sound RAM. Which of the $80 bytes is determined by the Address register ($F800). When read, the appropriate byte is returned. When written, the appropriate byte is set.

This RAM is used primarily for wavetables. The sound channel control registers are also set by writing to certain addresses in sound RAM:

Sound RAM $78 - Low Frequency

7  bit  0
---------
FFFF FFFF
|||| ||||
++++-++++- Low 8 bits of Frequency

Sound RAM $79 - Low Phase

7  bit  0
---------
FFFF FFFF
|||| ||||
++++-++++- Low 8 bits of Phase

Sound RAM $7A - Mid Frequency

7  bit  0
---------
FFFF FFFF
|||| ||||
++++-++++- Middle 8 bits of Frequency

Sound RAM $7B - Mid Phase

7  bit  0
---------
FFFF FFFF
|||| ||||
++++-++++- Middle 8 bits of Phase

Sound RAM $7C - High Frequency and Wave Length

7  bit  0
---------
LLLL LLFF
|||| ||||
|||| ||++- High 2 bits of Frequency
++++-++--- Length of waveform ((64-L)*4 4-bit samples)

Sound RAM $7D - High Phase

7  bit  0
---------
FFFF FFFF
|||| ||||
++++-++++- High 8 bits of Phase

The high bites of the 24-bit phase value directly determines the current sample position of the channel. Every time a channel is updated, the 18-bit frequency value is added to the 24-bit phase accumulator, which is stored in these three registers.

The phase registers may be written to immediately set the phase of the wave. It is good practice to set the frequency to 0 before doing so.

Sound RAM $7E - Wave Address

7  bit  0
---------
AAAA AAAA
|||| ||||
++++-++++- Address of waveform (in 4-bit samples)

Sound RAM $7F - Volume

7  bit  0
---------
.CCC VVVV
 ||| ||||
 ||| ++++- Linear Volume
 +++------ Enabled Channels (1+C)

Note 'C' is available on register $7F ONLY. Those bits have no effect in other registers.

• When C=0, only channel 8 enabled
• When C=1, channels 8 and 7 enabled
• When C=2, channels 8, 7, 6 enabled
• etc...

Other Channels

Above Sound RAM register descriptions ($78-$7F) are for the 8th channel. The other 7 channels are accessed via the same pattern, but each 8 bytes before the last:

Channel 8:  $78-$7F
Channel 7:  $70-$77
Channel 6:  $68-$6F
Channel 5:  $60-$67
Channel 4:  $58-$5F
Channel 3:  $50-$57
Channel 2:  $48-$4F
Channel 1:  $40-$47

Again note that the 'C' bits in the final register is only available at address $7F.

When channels are disabled, their registers are unused, and can be used for waveform data instead.

Operation

Each enabled channel cycles through its waveform at a rate determined by the 18-bit frequency value 'F'. Each step in the waveform is 4-bits wide, and the number of steps is determined by the 'L' bits ((64-L)*4). Two samples are stored to a byte, which is little-endian (unlike the Game Boy's wavetable channel).

The 'A' bits dictate where in the internal sound RAM the waveform starts. 'A' is the address in 4-bit samples, therefore a value of $02 would be the low 4 bits of address $01. A value of $03 would be the high 4 bits of address $01.

For a visual example, assume you have the following sound RAM:

$00:    00 00 00 A8 EC FE FF FF  EE AC 57 13 01 00 00 11
$10:    53 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00

And assume a channel has a 'A' value of $06, and a 'L' value of $39. That channel's wavetable would form a would-be sine wave, looking like the following:

F-     *****
E-   **     **
D-
C-  *         *
B-
A- *           *
9-
8-*
7-              *
6-
5-               *           *
4-
3-                *         *
2-
1-                 **     **
0-                   *****

The generated tone (in Hz) can be calculated from the following formula:

           F * 21477272.7272
Hz = -----------------------------
     $40000 * 45 * (C+1) * (64-L)*4

Where a 60 Hz tone would be a channel cycling through its entire waveform 60 times in one second.

A common method of emulating sound is to have the channel take another step through its wavetable every X CPU cycles. Therefore, an alternative formula:

    $40000 * 45 * (C+1)              $F0000 * (C+1)
X = -------------------    or    X = --------------
          12 * F                           F

Where X is the number of CPU cycles between steps in the channel's waveform.

Channel Update

The N163 does not internally mix its channels. Instead, each channel is output one at a time. It takes the N163 exactly 15 CPU cycles to update and output one channel. When multiple channels are used it will cycle between them. With 6 or fewer channels, the time to update all channels is a rate faster than any audible frequency, and the difference between this serial output and mixing cannot be heard, but for 8 channels it creates a very loud and apparent noise at the update rate. For a Famicom through RF output, this noise is attenuated during demodulation (which performs a lowpass filter), but through A/V output to a TV that does not filter high frequencies, it can be very unpleasant. Only two games used all 8 channels: King of Kings and Erika to Satoru no Yume Bouken.

Channels	Update Rate
1	119318 Hz
2	59659 Hz
3	39773 Hz
4	29830 Hz
5	23864 Hz
6	19886 Hz
7	17045 Hz
8	14915 Hz

The following is a speculative version of a single channel update, occurring every 15 CPU cycles:

* w[$80] = N163 internal memory
* sample(x) = (w[x/2] >> ((x&1)*4)) & $0F
* phase = (w[$7D] << 16) + (w[$7B] << 8) + w[$79]
* freq = ((w[$7C] & $03) << 16) + (w[$7A] << 8) + w[$78]
* length = 256 - (w[$7C] & $FC)
* offset = w[$7E]
* volume = w[$7F] & $0F

phase = (phase + freq) % (length << 16)
output = sample(((phase >> 16) + offset) & $FF) * volume

The output will be held until the next channel update. The 24-bit phase value will be stored back into w[$7D/$7B/$79].

References

• Namcot 106 Mapper Information by Goroh, ZW4, nori
• NES Music Format Spec by Kevin Horton, N106 info by Mamiya