INES Mapper 243: Difference between revisions

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(No readable solder pad on SA-020A.)
Line 36: Line 36:
               3: Single-screen: S0
               3: Single-screen: S0
Registers 0/1/3 are completely unused.
Registers 0/1/3 are completely unused.
==Protection and solder Pad ($4100, read)==
==Protection ($4100, read)==
  Mask: $C100
  Mask: $C100
   
   
Line 43: Line 43:
   .... .RRR
   .... .RRR
         +++- Inverse of previous index
         +++- Inverse of previous index
=Errata=
=Errata=
The '''SA-150''' PCB, denoted by [[INES Mapper 150]], connects the same ASIC differently, changing the meaning of the CHR-bank-related register bits.
The '''SA-150''' PCB, denoted by [[INES Mapper 150]], connects the same ASIC differently, changing the meaning of the CHR-bank-related register bits.

Revision as of 23:53, 7 December 2019

iNES Mapper 243 denotes the Sachen SA-020A circuit board. Using an eight-register ASIC with a fake "74LS374N" marking, it supports up to 128 KiB PRG-ROM, and 128 KiB of CHR-ROM. It is used for only one game, 美女拳 - Honey Peach (SA-006).

Banks

  • CPU $8000-$FFFF: switchable 32 KiB PRG-ROM bank
  • PPU $0000-$1FFF: switchable 8 KiB CHR-ROM bank
  • Nametable mirroring: switchable H/V/L-shaped/One-screen

Registers

Register Index ($4100, write)

Mask: $C101

D~7654 3210
  ---------
  .... .RRR
        +++- Select register number (Rx)

Register Data ($4101, write)

Mask: $C101

D~7654 3210
  ---------
  .... .RRR
        +++- Register data

D~7654 3210
  ---------
  .... ...A  R2: CHR A13
  .... ...C  R4: CHR A14
  .... ..PP  R5: PRG A16..A15
  .... ..DC  R6: CHR A16..A15
  ...  .MM.  R7: Nametable mirroring
              0: Vertical
              1: Horizontal
              2: L-shaped: S0-S1-S1-S1
              3: Single-screen: S0

Registers 0/1/3 are completely unused.

Protection ($4100, read)

Mask: $C100

D~7654 3210
  ---------
  .... .RRR
        +++- Inverse of previous index

Errata

The SA-150 PCB, denoted by INES Mapper 150, connects the same ASIC differently, changing the meaning of the CHR-bank-related register bits.

See also