INES Mapper 219: Difference between revisions
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(Source ref here rather than in edit notes, R3320) |
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Whichever of $8000, $8002 is last written decides what $8001 writes do. | Whichever of $8000, $8002 is last written decides what $8001 writes do. | ||
It appears to have MMC3-like | It appears to have [[MMC3#IRQ_latch_.28.24C000-.24DFFE.2C_even.29 | MMC3-like IRQ registers,]] as the implementation just falls through and uses those directly. | ||
Mask $E001 | Mask $E001 | ||
$C000 IRQ latch | $C000 IRQ latch | ||
| Line 19: | Line 18: | ||
$E000 IRQ disable | $E000 IRQ disable | ||
$E001 IRQ enable | $E001 IRQ enable | ||
CHR banking is very odd. The following bits are ORed together: | CHR banking is very odd. The following bits are ORed together: | ||
Latch: CBA98765.... [write <<4] | Latch: CBA98765.... [write << 4] | ||
Inner: .....7654321 [write >>1] | Inner: .....7654321 [write >> 1] | ||
and, if the bank is $0400 or $0C00, the | and, if the bank is $0400 or $0C00, the least significant bit is further ORed with 1. | ||
This has the effect of allowing consecutive writes to adjacent bank regs to get "sort of" a 2k bank. | |||
{| class="wikitable" | {| class="wikitable" | ||
| Line 54: | Line 54: | ||
| - || $1D || 7654321. || Inner 7 CHR bits for $1C00-$1FFF | | - || $1D || 7654321. || Inner 7 CHR bits for $1C00-$1FFF | ||
|} | |} | ||
==Sources== | ==Sources== | ||
[https://sourceforge.net/p/fceultra/code/3320/tree/fceu/trunk/src/boards/a9746.cpp FCEUX implementation] | [https://sourceforge.net/p/fceultra/code/3320/tree/fceu/trunk/src/boards/a9746.cpp FCEUX implementation] | ||
Revision as of 09:22, 14 October 2016
"A9746"
Banking
PRG: 4x8KiB (none fixed), 4 bits = 64KiB max CHR: 8x1KiB, 12 bits = 4MiB max
Registers
Mask: $E003 $8000 Select Register 1 $8002 Select Register 2 $8001 Control Register Whichever of $8000, $8002 is last written decides what $8001 writes do.
It appears to have MMC3-like IRQ registers, as the implementation just falls through and uses those directly.
Mask $E001 $C000 IRQ latch $C001 IRQ reload $E000 IRQ disable $E001 IRQ enable
CHR banking is very odd. The following bits are ORed together: Latch: CBA98765.... [write << 4] Inner: .....7654321 [write >> 1] and, if the bank is $0400 or $0C00, the least significant bit is further ORed with 1. This has the effect of allowing consecutive writes to adjacent bank regs to get "sort of" a 2k bank.
| $8000 write | $8002 write | bits | $8000 effect |
| $26 | - | ..PPPP.. | (reversed) bits of PRG bank $8000-$9FFF, central nibble only |
| $25 | - | ..PPPP.. | (reversed) bits of PRG bank $A000-$BFFF, central nibble only |
| $24 | - | ..PPPP.. | (reversed) bits of PRG bank $C000-$DFFF, central nibble only |
| $23 | - | ..PPPP.. | (reversed) bits of PRG bank $E000-$FFFF, central nibble only |
| - | $08-$1e even | CBA98765 | Outer CHR bit latch for any 1k bank, 8 bits |
| - | $09 | 7654321. | CHR bits for $0000-$03FF |
| - | $0B | 765432*. | Inner 7 CHR bits for $0400-$07FF (*least bit ORed to 1 regardless) |
| - | $0D | 7654321. | Inner 7 CHR bits for $0800-$0BFF |
| - | $0F | 765432*. | Inner 7 CHR bits for $0C00-$0FFF (*least bit ORed to 1 regardless) |
| - | $11 | 7654321. | Inner 7 CHR bits for $1000-$13FF |
| - | $15 | 7654321. | Inner 7 CHR bits for $1400-$17FF |
| - | $19 | 7654321. | Inner 7 CHR bits for $1800-$1BFF |
| - | $1D | 7654321. | Inner 7 CHR bits for $1C00-$1FFF |
