Fixed cycle delay: Difference between revisions

Revision as of 22:01, 13 March 2016

Delay code

Shortest possible CPU code that creates N cycles of delay, depending on constraints.

All branch instructions assume that no page wrap occurs.

Explanations on the requirements:

@zp_temp means you have a zeropage address that you can write random data into.
@rts12 means you know a memory address that contains byte $60 (RTS).
@rts14 means you know a memory address that contains a harmless 2-cycle instruction that fits your constraints (such as CLC, LDA #0, or NOP), followed by RTS.
@rts15 means you know a memory address that contains a JMP that jumps to another location that contains RTS.
Alternatively, @rts15 means you know a memory address that contains a harmless 3-cycle instruction that fits your constraints (such as LDA $00), followed by RTS.

0 cycles

0 bytes

1 cycle

Impossible

2 cycles

Canonical (1 bytes)

NOP

3 cycles

1 bytes

If you can clobber S:

PHA

2 bytes

If you can clobber Z, N and A:

LDA $00

If you can clobber Z, N and V:

BIT $00

If you have @zptemp:

STA @zptemp

If you can use unofficial opcodes:

NOP $00

Canonical (3 bytes)

JMP *+3

4 cycles

1 bytes

If you can clobber Z, N, A and S:

PLA

Synthetic (2 bytes)

{2-cycle delay} + {2-cycle delay}

5 cycles

Synthetic (2—4 bytes)

{2-cycle delay} + {3-cycle delay}

6 cycles

2 bytes

If you can clobber S:

PHA
PHA

Synthetic (3 bytes)

{2-cycle delay} + {4-cycle delay}

7 cycles

Canonical (2 bytes)

PHP
PLP

8 cycles

2 bytes

If you can clobber Z, N, A and S:

PLA
PLA

3 bytes

If you can clobber Z, N, A and X:

TSX
PLA
TXS

Synthetic (3—4 bytes)

{2-cycle delay} + {6-cycle delay}

9 cycles

Synthetic (3 bytes)

{2-cycle delay} + {7-cycle delay}

10 cycles

3 bytes

If you can clobber S:

PHA
PHP
PLP

4 bytes

Clobbers nothing, requires nothing:

PHP
BIT $00
PLP

11 cycles

3 bytes

If you can clobber Z, N, A and S:

PHA
PLA
PLA

Synthetic (4 bytes)

{2-cycle delay} + {9-cycle delay}

12 cycles

3 bytes

If you have @rts12:

JSR @rts12

If you can clobber Z, N, A and S:

PLA
PLA
PLA

4 bytes

If you can clobber Z and N:

ROL $00,X
ROR $00,X

Synthetic (4—5 bytes)

{2-cycle delay} + {10-cycle delay}

13 cycles

4 bytes

If you can clobber S:

PHA
PHA
PHP
PLP

Synthetic (5 bytes)

{2-cycle delay} + {11-cycle delay}

14 cycles

3 bytes

If you have @rts14:

JSR @rts14

Synthetic (4 bytes)

{7-cycle delay} + {7-cycle delay}

15 cycles

3 bytes

If you have @rts15:

JSR @rts15

4 bytes

If you can clobber S and you have @rts12:

PHA
JSR @rts12

If you can clobber Z, N, A and S:

PHA
PLA
PLA
PLA

5 bytes

If you can clobber Z, N and A and you have @rts12:

LDA $00
JSR @rts12

If you can clobber Z, N and X:

PHA
TSX
PLA
TXS
PLA

If you can clobber A and X:

PHP
TSX
PLA
TXS
PLP

If you can clobber Z, N and V and you have @rts12:

BIT $00
JSR @rts12

If you have @zptemp and you have @rts12:

STA @zptemp
JSR @rts12

If you can use unofficial opcodes and you have @rts12:

NOP $00
JSR @rts12

Synthetic (5—6 bytes)

{2-cycle delay} + {13-cycle delay}

16 cycles

4 bytes

If you can clobber Z, N, A and S:

PLA
PLA
PLA
PLA

Synthetic (4—5 bytes)

{2-cycle delay} + {14-cycle delay}

17 cycles

4 bytes

If you have @rts15:

NOP
JSR @rts15

If you can clobber S and you have @rts14:

PHA
JSR @rts14

5 bytes

If you can clobber Z, N and A and you have @rts14:

LDA $00
JSR @rts14

If you can clobber Z, N and V and you have @rts14:

BIT $00
JSR @rts14

If you have @zptemp and you have @rts14:

STA @zptemp
JSR @rts14

If you can clobber S:

PHA
PHP
PLP
PHP
PLP

If you can use unofficial opcodes and you have @rts14:

NOP $00
JSR @rts14

Synthetic (6 bytes)

{7-cycle delay} + {10-cycle delay}

18 cycles

4 bytes

If you can clobber S and you have @rts15:

PHA
JSR @rts15

If you can clobber Z, N, A and S and you have @rts14:

PLA
JSR @rts14

5 bytes

If you can clobber Z, N and A and you have @rts15:

LDA $00
JSR @rts15

If you can clobber Z, N and V and you have @rts15:

BIT $00
JSR @rts15

If you have @zptemp and you have @rts15:

STA @zptemp
JSR @rts15

If you can clobber S and you have @rts12:

PHA
PHA
JSR @rts12

If you can use unofficial opcodes and you have @rts15:

NOP $00
JSR @rts15

Synthetic (5—6 bytes)

{2-cycle delay} + {16-cycle delay}

19 cycles

4 bytes

If you can clobber Z, N, A and S and you have @rts15:

PLA
JSR @rts15

5 bytes

If you have @rts12:

PHP
PLP
JSR @rts12

If you have @rts15:

NOP
NOP
JSR @rts15

If you can clobber Z, N, A and S:

PHA
PLA
PLA
PLA
PLA

If you can clobber S and you have @rts14:

NOP
PHA
JSR @rts14

6 bytes

Clobbers nothing, requires nothing:

PHP
ROL $00,X
ROR $00,X
PLP

20 cycles

5 bytes

If you can clobber Z, N, A and S:

PLA
PLA
PLA
PLA
PLA

If you can clobber S and you have @rts14:

PHA
PHA
JSR @rts14

6 bytes

If you can clobber Z, N, A and X:

TSX
PLA
PLA
PLA
PLA
TXS

If you can clobber S:

PHA
PHA
PHP
PLP
PHP
PLP

Synthetic (5—7 bytes)

{2-cycle delay} + {18-cycle delay}

21 cycles

5 bytes

If you can clobber Z, N and Y:

LDY #4
@D:
DEY
BNE @D

If you can clobber Z, N and X:

LDX #4
@D:
DEX
BNE @D

If you can clobber S and you have @rts15:

PHA
PHA
JSR @rts15

Synthetic (5—6 bytes)

{7-cycle delay} + {14-cycle delay}

22 cycles

5 bytes

If you have @rts15:

PHP
PLP
JSR @rts15

If you can clobber Z, N, A and S and you have @rts14:

PLA
PLA
JSR @rts14

6 bytes

If you can clobber Z, N and Y:

LDY #3
@D:
NOP
DEY
BNE @D

If you can clobber Z, N and X:

LDX #3
@D:
NOP
DEX
BNE @D

If you can clobber S and you have @rts12:

PHA
PHP
PLP
JSR @rts12

7 bytes

If you have @rts12:

PHP
BIT $00
PLP
JSR @rts12

If you can clobber X:

PHP
PHA
TSX
PLA
TXS
PLA
PLP

Synthetic (6—8 bytes)

{2-cycle delay} + {20-cycle delay}

23 cycles

5 bytes

If you can clobber Z, N, A and S and you have @rts15:

PLA
PLA
JSR @rts15

6 bytes

If you can clobber Z, N, A and X and you have @rts15:

TSX
PLA
TXS
JSR @rts15

If you can clobber Z, N, A and S:

PHA
PLA
PLA
PLA
PLA
PLA

Synthetic (6—7 bytes)

{2-cycle delay} + {21-cycle delay}

24 cycles

6 bytes

If you have @rts12:

JSR @rts12
JSR @rts12

If you have @rts15:

NOP
PHP
PLP
JSR @rts15

If you can clobber Z, N, A and S:

PLA
PLA
PLA
PLA
PLA
PLA

If you can clobber S and you have @rts14:

PHA
PHP
PLP
JSR @rts14

7 bytes

If you can clobber Z, N, A and X:

TSX
PLA
PLA
PLA
PLA
PLA
TXS

If you have @rts14:

PHP
BIT $00
PLP
JSR @rts14

If you can clobber S:

PHA
PHP
PLP
PHP
PLP
PHP
PLP

Synthetic (8 bytes)

{7-cycle delay} + {17-cycle delay}

More

Bisqwit's 6502 delay_n macro set for ca65: http://bisqwit.iki.fi/src/6502-inline_delay.7z

@@ Line 4: / Line 4: @@
 All branch instructions assume that no page wrap occurs.
+Explanations on the requirements:
+* @zp_temp means you have a zeropage address that you can write random data into.
+* @rts12 means you know a memory address that contains byte $60 (<code>RTS</code>).
+* @rts14 means you know a memory address that contains a harmless 2-cycle instruction that fits your constraints (such as <code>CLC</code>, <code>LDA #0</code>, or <code>NOP</code>), followed by <code>RTS</code>.
+* @rts15 means you know a memory address that contains a <code>JMP</code> that jumps to another location that contains <code>RTS</code>.
+* Alternatively, @rts15 means you know a memory address that contains a harmless 3-cycle instruction that fits your constraints (such as <code>LDA $00</code>), followed by <code>RTS</code>.
 === 0 cycles ===
@@ Line 12: / Line 19: @@
 === 2 cycles ===
-byte: <code>NOP</code>
+==== Canonical (1 bytes) ====
+<pre>NOP</pre>
 === 3 cycles ===
+==== 1 bytes ====
+''If you can clobber S'':<br>
+<pre>PHA</pre>
-If you can clobber S:<br>
+==== 2 bytes ====
-byte: <code>PHA</code>
+''If you can clobber Z, N and A'':<br>
+<pre>LDA $00</pre>
-If you have a zeropage address that you can write random data into (example: $00):<br>
+''If you can clobber Z, N and V'':<br>
-bytes: <code>STA $00</code>
+<pre>BIT $00</pre>
-If you can use unofficial opcodes:<br>
+''If you have @zptemp'':<br>
-bytes: <code>NOP $00</code> (04 00)
+<pre>STA @zptemp</pre>
-If you can clobber Z, N and V:<br>
+''If you can use unofficial opcodes'':<br>
-bytes: <code>BIT $00</code>
+<pre>NOP $00</pre>
-If you can clobber Z, N and A:<br>
+==== Canonical (3 bytes) ====
-bytes: <code>LDA $00</code>
+<pre>JMP *+3</pre>
-Else:<br>
-bytes: <code>JMP * + 3</code>
 === 4 cycles ===
-If you can clobber Z, N, S and A:<br>
+==== 1 bytes ====
-byte: <code>PLA</code>
+''If you can clobber Z, N, A and S'':<br>
+<pre>PLA</pre>
-If you can use unofficial opcodes:<br>
+==== Synthetic (2 bytes) ====
-bytes, 1 instruction: <code>NOP $00,X</code> (14 00)
+{2-cycle delay} + {2-cycle delay}
-Else:<br>
-bytes, 2 instructions: 2 × <code>NOP</code>
 === 5 cycles ===
-―4 bytes: <code>NOP</code> + {3-cycle delay code}
+==== Synthetic (2&mdash;4 bytes) ====
+{2-cycle delay} + {3-cycle delay}
 === 6 cycles ===
-bytes: 3 × <code>NOP</code>
+==== 2 bytes ====
+''If you can clobber S'':<br>
+<pre>PHA
+PHA</pre>
+==== Synthetic (3 bytes) ====
+{2-cycle delay} + {4-cycle delay}
 === 7 cycles ===
-bytes: <code>PHP<br>
+==== Canonical (2 bytes) ====
-PLP</code>
+<pre>PHP
+PLP</pre>
 === 8 cycles ===
-If you can clobber Z, N, S and A:<br>
+==== 2 bytes ====
-bytes: 2 × <code>PLA</code>
+''If you can clobber Z, N, A and S'':<br>
+<pre>PLA
+PLA</pre>
-If you can clobber Z, N, X and A:<br>
+==== 3 bytes ====
-bytes: <code>TSX<br>
+''If you can clobber Z, N, A and X'':<br>
-PLA<br>
+<pre>TSX
-TXS</code>
+PLA
+TXS</pre>
+==== Synthetic (3&mdash;4 bytes) ====
+{2-cycle delay} + {6-cycle delay}
-Else:<br>
-bytes: 4 × <code>NOP</code>
 === 9 cycles ===
-bytes: {7-cycle delay code} + {2-cycle delay code}
+==== Synthetic (3 bytes) ====
+{2-cycle delay} + {7-cycle delay}
 === 10 cycles ===
+==== 3 bytes ====
-If you can clobber S:<br>
+''If you can clobber S'':<br>
-bytes: <code>PHA
+<pre>PHA
 PHP
-PLP</code>
+PLP</pre>
-Else:<br>
+==== 4 bytes ====
-bytes: <code>PHP
+''Clobbers nothing, requires nothing'':<br>
+<pre>PHP
 BIT $00
-PLP</code>
+PLP</pre>
 === 11 cycles ===
-―4 bytes: {7-cycle delay code} + {4-cycle delay code}
+==== 3 bytes ====
+''If you can clobber Z, N, A and S'':<br>
+<pre>PHA
+PLA
+PLA</pre>
+==== Synthetic (4 bytes) ====
+{2-cycle delay} + {9-cycle delay}
 === 12 cycles ===
-If you know a memory address that contains byte $60 (<code>RTS</code>):<br>
+==== 3 bytes ====
-bytes: <code>JSR location</code>
+''If you have @rts12'':<br>
+<pre>JSR @rts12</pre>
-If you can clobber Z, N, S and A:<br>
+''If you can clobber Z, N, A and S'':<br>
-bytes: 3 × <code>PLA</code>
+<pre>PLA
+PLA
+PLA</pre>
-If you can clobber Z and N (note that this does not change C or memory, and that it does not depend on value of X):<br>
+==== 4 bytes ====
-bytes: <code>ROL $00,X<br>
+''If you can clobber Z and N'':<br>
-ROR $00,X</code>
+<pre>ROL $00,X
+ROR $00,X</pre>
+==== Synthetic (4&mdash;5 bytes) ====
+{2-cycle delay} + {10-cycle delay}
-Else:<br>
-―6 bytes: {7-cycle delay code} + {5-cycle delay code}
 === 13 cycles ===
-bytes: {7-cycle delay code} + {6-cycle delay code}
+==== 4 bytes ====
+''If you can clobber S'':<br>
+<pre>PHA
+PHA
+PHP
+PLP</pre>
+==== Synthetic (5 bytes) ====
+{2-cycle delay} + {11-cycle delay}
 === 14 cycles ===
-If you know a memory address that contains a harmless 2-cycle instruction that fits your constraints (such as <code>CLC</code>, <code>LDA #0</code>, or <code>NOP</code>), followed by <code>RTS</code>:<br>
+==== 3 bytes ====
-bytes: <code>JSR location</code>
+''If you have @rts14'':<br>
+<pre>JSR @rts14</pre>
+==== Synthetic (4 bytes) ====
+{7-cycle delay} + {7-cycle delay}
-Else:<br>
-bytes: 2 × {7-cycle delay code}
 === 15 cycles ===
-If you know a memory address that contains a <code>JMP</code> that jumps to another location that contains <code>RTS</code>:<br>
+==== 3 bytes ====
-bytes: <code>JSR location</code>
+''If you have @rts15'':<br>
+<pre>JSR @rts15</pre>
-If you know a memory address that contains a harmless 3-cycle instruction that fits your constraints (such as <code>LDA $00</code>), followed by <code>RTS</code>:<br>
+==== 4 bytes ====
-bytes: <code>JSR location</code>
+''If you can clobber S and you have @rts12'':<br>
+<pre>PHA
+JSR @rts12</pre>
+''If you can clobber Z, N, A and S'':<br>
+<pre>PHA
+PLA
+PLA
+PLA</pre>
+==== 5 bytes ====
+''If you can clobber Z, N and A and you have @rts12'':<br>
+<pre>LDA $00
+JSR @rts12</pre>
+''If you can clobber Z, N and X'':<br>
+<pre>PHA
+TSX
+PLA
+TXS
+PLA</pre>
+''If you can clobber A and X'':<br>
+<pre>PHP
+TSX
+PLA
+TXS
+PLP</pre>
+''If you can clobber Z, N and V and you have @rts12'':<br>
+<pre>BIT $00
+JSR @rts12</pre>
+''If you have @zptemp and you have @rts12'':<br>
+<pre>STA @zptemp
+JSR @rts12</pre>
+''If you can use unofficial opcodes and you have @rts12'':<br>
+<pre>NOP $00
+JSR @rts12</pre>
+==== Synthetic (5&mdash;6 bytes) ====
+{2-cycle delay} + {13-cycle delay}
-Else:<br>
-―6 bytes: {8-cycle delay code} + {7-cycle delay code}
 === 16 cycles ===
-If you can clobber Z, N, S and A:<br>
+==== 4 bytes ====
-bytes: 4 × <code>PLA</code>
+''If you can clobber Z, N, A and S'':<br>
+<pre>PLA
+PLA
+PLA
+PLA</pre>
+==== Synthetic (4&mdash;5 bytes) ====
+{2-cycle delay} + {14-cycle delay}
-Else:<br>
-―5 bytes: {14-cycle delay code} + {2-cycle delay code}
 === 17 cycles ===
-If your 15-cycle delay code is 3 bytes long:<br>
+==== 4 bytes ====
-bytes: {15-cycle delay code} + {2-cycle delay code}
+''If you have @rts15'':<br>
+<pre>NOP
+JSR @rts15</pre>
+''If you can clobber S and you have @rts14'':<br>
+<pre>PHA
+JSR @rts14</pre>
+==== 5 bytes ====
+''If you can clobber Z, N and A and you have @rts14'':<br>
+<pre>LDA $00
+JSR @rts14</pre>
+''If you can clobber Z, N and V and you have @rts14'':<br>
+<pre>BIT $00
+JSR @rts14</pre>
+''If you have @zptemp and you have @rts14'':<br>
+<pre>STA @zptemp
+JSR @rts14</pre>
+''If you can clobber S'':<br>
+<pre>PHA
+PHP
+PLP
+PHP
+PLP</pre>
+''If you can use unofficial opcodes and you have @rts14'':<br>
+<pre>NOP $00
+JSR @rts14</pre>
+==== Synthetic (6 bytes) ====
+{7-cycle delay} + {10-cycle delay}
-Else:<br>
-―7 bytes: {10-cycle delay code} + {7-cycle delay code}
 === 18 cycles ===
-―6 bytes: {16-cycle delay code} + {2-cycle delay code}
+==== 4 bytes ====
+''If you can clobber S and you have @rts15'':<br>
+<pre>PHA
+JSR @rts15</pre>
+''If you can clobber Z, N, A and S and you have @rts14'':<br>
+<pre>PLA
+JSR @rts14</pre>
+==== 5 bytes ====
+''If you can clobber Z, N and A and you have @rts15'':<br>
+<pre>LDA $00
+JSR @rts15</pre>
+''If you can clobber Z, N and V and you have @rts15'':<br>
+<pre>BIT $00
+JSR @rts15</pre>
+''If you have @zptemp and you have @rts15'':<br>
+<pre>STA @zptemp
+JSR @rts15</pre>
+''If you can clobber S and you have @rts12'':<br>
+<pre>PHA
+PHA
+JSR @rts12</pre>
+''If you can use unofficial opcodes and you have @rts15'':<br>
+<pre>NOP $00
+JSR @rts15</pre>
+==== Synthetic (5&mdash;6 bytes) ====
+{2-cycle delay} + {16-cycle delay}
 === 19 cycles ===
-―8 bytes: {12-cycle delay code} + {7-cycle delay code}
+==== 4 bytes ====
+''If you can clobber Z, N, A and S and you have @rts15'':<br>
+<pre>PLA
+JSR @rts15</pre>
+==== 5 bytes ====
+''If you have @rts12'':<br>
+<pre>PHP
+PLP
+JSR @rts12</pre>
+''If you have @rts15'':<br>
+<pre>NOP
+NOP
+JSR @rts15</pre>
+''If you can clobber Z, N, A and S'':<br>
+<pre>PHA
+PLA
+PLA
+PLA
+PLA</pre>
+''If you can clobber S and you have @rts14'':<br>
+<pre>NOP
+PHA
+JSR @rts14</pre>
+==== 6 bytes ====
+''Clobbers nothing, requires nothing'':<br>
+<pre>PHP
+ROL $00,X
+ROR $00,X
+PLP</pre>
 === 20 cycles ===
-If you can clobber Z, N, S and A:<br>
+==== 5 bytes ====
-bytes: 5 × <code>PLA</code>
+''If you can clobber Z, N, A and S'':<br>
+<pre>PLA
+PLA
+PLA
+PLA
+PLA</pre>
-If your 18-cycle delay code is 5 bytes long:<br>
+''If you can clobber S and you have @rts14'':<br>
-bytes: {18-cycle delay code} + {2-cycle delay code}
+<pre>PHA
+PHA
+JSR @rts14</pre>
+==== 6 bytes ====
+''If you can clobber Z, N, A and X'':<br>
+<pre>TSX
+PLA
+PLA
+PLA
+PLA
+TXS</pre>
+''If you can clobber S'':<br>
+<pre>PHA
+PHA
+PHP
+PLP
+PHP
+PLP</pre>
+==== Synthetic (5&mdash;7 bytes) ====
+{2-cycle delay} + {18-cycle delay}
-Else:<br>
-bytes: {13-cycle delay code} + {7-cycle delay code}
 === 21 cycles ===
-If your 14-cycle delay code is 3 bytes long:<br>
+==== 5 bytes ====
-bytes: {14-cycle delay code} + {7-cycle delay code}
+''If you can clobber Z, N and Y'':<br>
+<pre>LDY #4
+@D:
+DEY
+BNE @D</pre>
+''If you can clobber Z, N and X'':<br>
+<pre>LDX #4
+@D:
+DEX
+BNE @D</pre>
+''If you can clobber S and you have @rts15'':<br>
+<pre>PHA
+PHA
+JSR @rts15</pre>
-If you can clobber Z, N and <index register> (here, assumes X):<br>
+==== Synthetic (5&mdash;6 bytes) ====
-bytes: <code>LDX #4<br>
+{7-cycle delay} + {14-cycle delay}
-loop: DEX<br>
-BNE loop</code>
-Else:<br>
-bytes: {14-cycle delay code} + {7-cycle delay code}
 === 22 cycles ===
+==== 5 bytes ====
+''If you have @rts15'':<br>
+<pre>PHP
+PLP
+JSR @rts15</pre>
+''If you can clobber Z, N, A and S and you have @rts14'':<br>
+<pre>PLA
+PLA
+JSR @rts14</pre>
+==== 6 bytes ====
+''If you can clobber Z, N and Y'':<br>
+<pre>LDY #3
+@D:
+NOP
+DEY
+BNE @D</pre>
+''If you can clobber Z, N and X'':<br>
+<pre>LDX #3
+@D:
+NOP
+DEX
+BNE @D</pre>
+''If you can clobber S and you have @rts12'':<br>
+<pre>PHA
+PHP
+PLP
+JSR @rts12</pre>
+==== 7 bytes ====
+''If you have @rts12'':<br>
+<pre>PHP
+BIT $00
+PLP
+JSR @rts12</pre>
-If you can clobber Z, N and <index register> (here, assumes X):<br>
+''If you can clobber X'':<br>
-bytes: <code>LDX #3<br>
+<pre>PHP
-loop: NOP<br>
+PHA
-DEX<br>
+TSX
-BNE loop</code>
+PLA
+TXS
+PLA
+PLP</pre>
+==== Synthetic (6&mdash;8 bytes) ====
+{2-cycle delay} + {20-cycle delay}
-Else:
-―8 bytes: {15-cycle delay code} + {7-cycle delay code}
 === 23 cycles ===
-If your 16-cycle delay code is 4 bytes long:<br>
+==== 5 bytes ====
-bytes: {16-cycle delay code} + {7-cycle delay code}
+''If you can clobber Z, N, A and S and you have @rts15'':<br>
+<pre>PLA
+PLA
+JSR @rts15</pre>
-If your 21-cycle delay code is 5 bytes long:<br>
+==== 6 bytes ====
-bytes: {21-cycle delay code} + {2-cycle delay code}
+''If you can clobber Z, N, A and X and you have @rts15'':<br>
+<pre>TSX
+PLA
+TXS
+JSR @rts15</pre>
+''If you can clobber Z, N, A and S'':<br>
+<pre>PHA
+PLA
+PLA
+PLA
+PLA
+PLA</pre>
+==== Synthetic (6&mdash;7 bytes) ====
+{2-cycle delay} + {21-cycle delay}
-Else:
-―7 bytes: {15-cycle delay code} + {7-cycle delay code}
 === 24 cycles ===
-If you can clobber Z, N, S and A:<br>
+==== 6 bytes ====
-bytes: 6 × <code>PLA</code>
+''If you have @rts12'':<br>
+<pre>JSR @rts12
+JSR @rts12</pre>
-If your 17-cycle delay code is 4 bytes long:<br>
+''If you have @rts15'':<br>
-bytes: {17-cycle delay code} + {7-cycle delay code}
+<pre>NOP
+PHP
+PLP
+JSR @rts15</pre>
-Option:<br>
+''If you can clobber Z, N, A and S'':<br>
-―9 bytes: {22-cycle delay code} + {2-cycle delay code}
+<pre>PLA
+PLA
+PLA
+PLA
+PLA
+PLA</pre>
-Option:<br>
+''If you can clobber S and you have @rts14'':<br>
-―9 bytes: {17-cycle delay code} + {7-cycle delay code}
+<pre>PHA
+PHP
+PLP
+JSR @rts14</pre>
+==== 7 bytes ====
+''If you can clobber Z, N, A and X'':<br>
+<pre>TSX
+PLA
+PLA
+PLA
+PLA
+PLA
+TXS</pre>
+''If you have @rts14'':<br>
+<pre>PHP
+BIT $00
+PLP
+JSR @rts14</pre>
+''If you can clobber S'':<br>
+<pre>PHA
+PHP
+PLP
+PHP
+PLP
+PHP
+PLP</pre>
+==== Synthetic (8 bytes) ====
+{7-cycle delay} + {17-cycle delay}
 == More ==
 Bisqwit's 6502 delay_n macro set for ca65: http://bisqwit.iki.fi/src/6502-inline_delay.7z