APU

The NES APU is the audio processing unit in the NES console which generates sound for games. It is implemented in the RP2A03 (NTSC) and RP2A07 (PAL) chips. Its registers are mapped in the range $4000-$4013, $4015 and $4017.

Overview

The APU has five channels: two pulse wave generators, a triangle wave, noise, and a delta modulation channel for playing DPCM samples.

Each channel has a variable-rate timer clocking a waveform generator, and various modulators driven by low-frequency clocks from the frame counter. The DMC plays samples while the other channels play waveforms. Each sub-unit of a channel generally runs independently and in parallel to other units, and modification of a channel's parameter usually affects only one sub-unit and doesn't take effect until that unit's next internal cycle begins.

The read/write status register allows channels to be enabled and disabled, and their current length counter status to be queried.

The outputs from all the channels are combined using a non-linear mixing scheme.

Notes

• This reference describes the abstract operation of the APU. The exact hardware implementation is not necessarily relevant to an emulator, but the Visual 2A03 project can be used to determine detailed information about the hardware implementation.

• The Famicom had an audio return loop on its catridge connector allowing extra audio from individual cartridges. See Expansion audio for details on the audio produced by various mappers.

• For a basic usage guide to the APU, see APU basics, or Nerdy Nights: APU overview.

Specification

Registers

Registers	Channel	Units
$4000-$4003	Pulse 1	Timer, Length Counter, Envelope, Sweep
$4004-$4007	Pulse 2	Timer, Length Counter, Envelope, Sweep
$4008-$400B	Triangle	Timer, Length Counter, linear counter
$400C-$400F	Noise	Timer, Length Counter, Envelope, shift register w/ feedback
$4010-$4013	DMC	Timer, memory reader, sample buffer, output unit
$4015	All	Channel enable and length counter status
$4017	All	Frame counter

Pulse ($4000-4007)

• See APU Pulse

Triangle ($4008-400B)

• See APU Triangle

Noise ($400C-400F)

• See APU Noise

DMC ($4010-4013)

• See APU DMC

The delta modulation channel outputs a 7-bit PCM signal from a counter that can be driven by DPCM samples.

$4010	IL-- RRRR	IRQ enable (I), loop (L), frequency (R)
$4011	-DDD DDDD	Load counter (D)
$4012	AAAA AAAA	Sample address (A)
$4013	LLLL LLLL	Sample length (L)

• DPCM samples are stored as a stream of 1-bit deltas that control the 7-bit PCM counter that the channel outputs. A bit of 1 will increment the counter, 0 will decrement, and it will clamp rather than overflow if the 7-bit range is exceeded.

• DPCM samples may loop if the loop flag in $4010 is set, and the DMC may be used to generate an IRQ when the end of the sample is reached if its IRQ flag is set.

• The playback rate is controlled by register $4010 with a 4-bit frequency index value (see APU DMC for frequency lookup tables).

• DPCM samples must begin in the memory range $C000-FFFF at an address set by register $4012 (address = %11AAAAAA.AA000000).

• The length of the sample in bytes is set by register $4013 (length = %LLLL.LLLL0001).

Other Uses

• The $4011 register can be used to play PCM samples directly by setting the counter value at a high frequency. Because this requires intensive use of the CPU, when used in games all other gameplay is usually halted to facilitate this.

• Because of the APU's nonlinear mixing, a high value in the PCM counter reduces the volume of the triangle and noise channels. This is sometimes used to apply limited volume control to the triangle channel (e.g. Super Mario Bros. adjusts the counter between levels to accomplish this).

• The DMC's IRQ can be used as an IRQ based timer when the mapper used does not have one available.

Status ($4015)

The status register is used to enable and disable individual channels, control the DMC, and can read the status of length counters and APU interrupts.

$4017 write	---D NT21	Enable DMC (D), noise (N), triangle (T), and pulse channels (2/1)

• Writing a zero to any of the channel enable bits will silence that channel and immediately set its length counter to 0.
• If the DMC bit is clear, the DMC bytes remaining will be set to 0 and the DMC will silence when it empties.
• If the DMC bit is set, the DMC sample will be restarted only if its bytes remaining is 0.
• Writing to this register clears the DMC interrupt flag.

$4017 read	IF-D NT21	DMC interrupt (I), frame interrupt (F), DMC active (D), length counter > 0 (N/T/2/1)

• Reading this register clears the frame interrupt flag (but not the DMC interrupt flag).
• If an interrupt flag was set at the same moment of the read, it will read back as 1 but it will not be cleared.

Frame Counter ($4017)

• See APU Frame Counter

$4017	MI-- ----	Mode (M, 0 = 4-step, 1 = 5-step), IRQ inhibit flag (I)

The frame counter is controlled by register $4017, and it drives the envelope, sweep, and length units on the pulse, triangle and noise channels. It ticks approximately 4 times per frame (240Hz), and executes either a 4 or 5 step sequence, depending how it is configured. It may optionally issue an IRQ on the last tick of each sequence.

The following diagram illustrates the two modes, selected by bit 7 of $4017:

mode 0:    mode 1:       function
---------  -----------  -----------------------------
 - - - f    - - - - -    IRQ (if bit 6 is clear)
 - l - l    l - l - -    Length counter and sweep
 e e e e    e e e e -    Envelope and linear counter

Both the 4 and 5-step modes operate at the same rate, but because the 5-step mode has an extra step, the effective update rate for individual units is slower in that mode (total update taking ~60Hz vs ~48Hz). Writing to $4017 will restart the sequence almost immediately (2 or 3 CPU cycles delay). Writing $4017 with bit 7 set will immediately clock all of its controlled units at the beginning of the 5-step sequence, but with bit 7 clear only the envelope and linear counter will be clocked.

Note that the frame counter is not exactly synchronized with the PPU NMI; it runs independently at a consistent rate which is approximately 240Hz. Some games (e.g. Super Mario Bros., Zelda) manually synchronize it by writing $C0 or $FF to $4017 once per frame.

Length Counter

• See APU Length Counter

The pulse, triangle, and noise channels each have their own length counter unit. It is clocked twice per sequence, and counts down to zero if enabled. When the length counter reaches zero the channel is silenced. It is reloaded by writing a 5-bit value to the appropriate channel's length counter register, which will loads a value from the following table:

      |  0    1   2   3   4   5   6   7    8   9   A   B   C   D   E   F
------+-----------------------------------------------------------------
00-0F | 10, 254, 20,  2, 40,  4, 80,  6, 160,  8, 60, 10, 14, 12, 26, 14
10-1F | 12,  16, 24, 18, 48, 20, 96, 22, 192, 24, 72, 26, 16, 28, 32, 30

The triangle channel has an additional linear counter unit which is clocked four times per sequence (like the envelope of the other channels). It functions independently of the length counter, and will also silence the triangle channel when it reaches zero.

Mixer

• See APU Mixer

Glossary

• All APU channels have some form of frequency control. The term frequency is used where larger register value(s) correspond with higher frequencies, and the term period is used where smaller register value(s) correspond with higher frequencies.

• In the block diagrams, a gate takes the input on the left and outputs it on the right, unless the control input on top tells the gate to ignore the input and always output 0.

• Some APU units use one or more of the following building blocks:

• • A divider outputs a clock every n input clocks, where n is the divider's period. It contains a counter which is decremented on the arrival of each clock. When the counter reaches 0, it is reloaded with the period and an output clock is generated. A divider can also be forced to reload its counter immediately, but this does not output a clock. When a divider's period is changed, the current count is not affected.

• • A divider may be implemented as a down counter (5, 4, 3, ...) or as a linear feedback shift register (LFSR). The dividers in the pulse and triangle channels are linear down-counters. The dividers for noise, DMC, and the APU Frame Counter are implemented as LFSRs to save gates compared to the equivalent down counter.

• • A sequencer continuously loops over a sequence of values or events. When clocked, the next item in the sequence is generated.

• • A timer is used in each of the five channels to control the sound frequency. It contains a divider which is clocked by the CPU clock. The triangle channel's timer is clocked on every CPU cycle, but the pulse, noise, and DMC timers are clocked only on every second CPU cycle and thus produce only even periods.

References

• Blargg's NES APU Reference.
• Brad Taylor's 2A03 Technical Reference.