INES Mapper 034: Difference between revisions

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{{DEFAULTSORT:034}}[[Category:iNES Mappers]][[Category:Mappers with CHR RAM]][[Category:Mappers with bus conflicts]][[Category:Nintendo licensed mappers]][[Category:NES 2.0 mappers with submappers]]
{{DEFAULTSORT:034}}[[Category:iNES Mappers]][[Category:Mappers with CHR RAM]][[Category:Mappers with bus conflicts]][[Category:Nintendo licensed mappers]][[Category:NES 2.0 mappers with submappers]]
 
'''iNES Mapper 034''' denotes the unrelated [[#NINA-001/NINA-002|NINA-001/NINA-002]] and [[#BNROM|BNROM]] circuit boards. The NES 2.0 Submapper differentiates the two:
[[iNES Mapper 034]] is used to designate both the [[BNROM]] and [[NINA-001]] boards. These two boards are unrelated, but have unfortunately been grouped into the same mapper.
* '''Submapper 1''' denotes the NINA-001/NINA-002 circuit board,
 
* '''Submapper 2''' denotes the BNROM circuit board.
Many emulators implement both sets of registers simultaneously, which is safe for the two existing commercial games.
In the absence of valid submapper information, mapper 34 .NES files should be considered BNROM when the CHR-ROM size is 0-8 KiB, and NINA-001/NINA-002 when the CHR-ROM size is above 8 KiB.
 
=NINA-001/NINA-002=
If the emulator wishes to separate the two implementations, they may check the number of CHR banks present: BNROM should be used when there is 0 to 8 KiB of CHR, and NINA-001 should be used otherwise. The [[NES 2.0]] header with a [[NES_2.0_submappers#034:_BNROM_/_NINA-001|submapper]] can be used to force use of specific board behavior.
The NINA-001 PCB supports 64 KiB of PRG-ROM capacity and uses a microcontroller to disable the [[CIC]]. The NINA-002 PCB increases PRG-ROM capacity to 128 KiB and uses a stun circuit to disable the CIC.
 
==Banks==
Developers wishing to use mapper 34 should strictly use only the BNROM or only the NINA-001 registers in a single ROM, and be careful not to accidentally write to the other set of registers.
* CPU $6000-$7FFF: 8 KiB of unbanked PRG-RAM.
 
* CPU $8000-$FFFF: 32 KiB window into 64 KiB (NINA-001)/128 KiB (NINA-002) of PRG-ROM
[[iNES Mapper 241]] is a variation of BxROM with 8k PRG-RAM at $6000, which avoids having the conflicting NINA-001 registers in that location.
* PPU $0000-$0FFF: 4 KiB window into 64 KiB of CHR-ROM
 
* PPU $1000-$1FFF: 4 KiB window into 64 KiB of CHR-ROM
== BNROM ==
* Nametable arrangement: Fixed; solder pad selects between Horizontal and Vertical
See: [[BNROM]]
==Registers==
 
The registers overlapping PRG-RAM at the same addresses mean that reading the register's address returns the last value written to the PRG-RAM, which is also the last value written to the register.
* PRG ROM size: 128 KB (mapper implementations may support up to 512 KB or 8 MB)
===PRG Bank Select ($7FFD, write)===
* PRG ROM bank size: 32 KB
  D~[.... ..BA] A~[0111 1111 1111 1101]
* PRG RAM: None
          ++- PRG A16..A15 (32 KiB bank)
* CHR capacity: 8 KB RAM
The power-on value is undefined; games should have a reset vector and handler in all PRG-ROM banks.
* CHR bank size: Not bankswitched
===CHR Bank Select 0 ($7FFE, write)===
* Nametable [[mirroring]]: Solder pads select vertical or horizontal mirroring
D~[.... DCBA] A~[0111 1111 1111 1110]
* Subject to [[bus conflict]]s: Yes
        ++++- CHR A15..A12 (4 KiB bank) at PPU $0000
 
===CHR Bank Select 1 ($7FFF, write)===
Games:
D~[.... DCBA] A~[0111 1111 1111 1111]
* ''Deadly Towers'' (''Mashou'')
        ++++- CHR A15..A12 (4 KiB bank) at PPU $1000
 
=BNROM=
Registers:
==Banks==
              7 bit  0
* CPU $8000-$FFFF: 32 KiB window into 128 KiB of PRG-ROM
              ---------
* PPU $0000-$1FFF: 8 KiB of unbanked CHR-RAM/-ROM
  $8000-FFFF: .... ..PP - Select 32 KB PRG ROM bank
* Nametable arrangement: Fixed; solder pad selects between Horizontal and Vertical
 
==Register: Bank Select ($8000-$FFFF, write)==
Emulators commonly support either a 4-bit or 8-bit register, enabling up to 512 KB or 8 MB PRG ROM.
D~[.... ..BA] A~[1... .... .... ....]
This variant may be referred to as '''BxROM'''.
          ++- PRG A16..A15 (32 KiB bank)
 
* The power-on value is undefined; games should have a reset vector and handler in all PRG-ROM banks.
== NINA-001 ==
* The original BNROM board is always subject to AND-type bus conflicts: the effective value is the value being written bitwise-AND'd with the PRG-ROM content at the address being written to.
See: [[NINA-001]]
==See also==
 
[[iNES Mapper 241]] is a variation of BxROM with 8 KiB PRG-RAM at CPU $6000-$7FFF, avoids bus conflicts, and optionally supports an LPC speech chip.
* PRG ROM size: 64 KB
* PRG ROM bank size: 32 KB
* PRG RAM: 8 KB, not battery backed
* CHR ROM capacity: 64 KB ROM
* CHR bank size: 4 KB
* Nametable [[mirroring]]: Hardwired to vertical mirroring
* Subject to [[bus conflict]]s: No
 
Games:
* ''Impossible Mission 2''
 
Registers:
        7  bit  0
        ---------
  $7FFD: .... ...P - Select 32 KB PRG ROM bank
  $7FFE: .... CCCC - Select 4 KB CHR bank at $0000
  $7FFF: .... CCCC - Select 4 KB CHR bank at $1000
 
== See also ==
 
*[http://nesdev.org/mappers.zip Comprehensive NES Mapper Document] by \Firebug\, information about mapper's initial state is inaccurate.

Revision as of 13:52, 8 February 2025

iNES Mapper 034 denotes the unrelated NINA-001/NINA-002 and BNROM circuit boards. The NES 2.0 Submapper differentiates the two:

  • Submapper 1 denotes the NINA-001/NINA-002 circuit board,
  • Submapper 2 denotes the BNROM circuit board.

In the absence of valid submapper information, mapper 34 .NES files should be considered BNROM when the CHR-ROM size is 0-8 KiB, and NINA-001/NINA-002 when the CHR-ROM size is above 8 KiB.

NINA-001/NINA-002

The NINA-001 PCB supports 64 KiB of PRG-ROM capacity and uses a microcontroller to disable the CIC. The NINA-002 PCB increases PRG-ROM capacity to 128 KiB and uses a stun circuit to disable the CIC.

Banks

  • CPU $6000-$7FFF: 8 KiB of unbanked PRG-RAM.
  • CPU $8000-$FFFF: 32 KiB window into 64 KiB (NINA-001)/128 KiB (NINA-002) of PRG-ROM
  • PPU $0000-$0FFF: 4 KiB window into 64 KiB of CHR-ROM
  • PPU $1000-$1FFF: 4 KiB window into 64 KiB of CHR-ROM
  • Nametable arrangement: Fixed; solder pad selects between Horizontal and Vertical

Registers

The registers overlapping PRG-RAM at the same addresses mean that reading the register's address returns the last value written to the PRG-RAM, which is also the last value written to the register.

PRG Bank Select ($7FFD, write)

D~[.... ..BA] A~[0111 1111 1111 1101]
          ++- PRG A16..A15 (32 KiB bank)

The power-on value is undefined; games should have a reset vector and handler in all PRG-ROM banks.

CHR Bank Select 0 ($7FFE, write)

D~[.... DCBA] A~[0111 1111 1111 1110]
        ++++- CHR A15..A12 (4 KiB bank) at PPU $0000

CHR Bank Select 1 ($7FFF, write)

D~[.... DCBA] A~[0111 1111 1111 1111]
        ++++- CHR A15..A12 (4 KiB bank) at PPU $1000

BNROM

Banks

  • CPU $8000-$FFFF: 32 KiB window into 128 KiB of PRG-ROM
  • PPU $0000-$1FFF: 8 KiB of unbanked CHR-RAM/-ROM
  • Nametable arrangement: Fixed; solder pad selects between Horizontal and Vertical

Register: Bank Select ($8000-$FFFF, write)

D~[.... ..BA] A~[1... .... .... ....]
          ++- PRG A16..A15 (32 KiB bank)
  • The power-on value is undefined; games should have a reset vector and handler in all PRG-ROM banks.
  • The original BNROM board is always subject to AND-type bus conflicts: the effective value is the value being written bitwise-AND'd with the PRG-ROM content at the address being written to.

See also

iNES Mapper 241 is a variation of BxROM with 8 KiB PRG-RAM at CPU $6000-$7FFF, avoids bus conflicts, and optionally supports an LPC speech chip.

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