Status flags

The flags register, also called processor status or just P, is one of the six architectural registers on the 6502 family CPU. It is composed of six one-bit registers; instructions modify one or more bits and leave others unchanged.

Flags

Instructions that save or restore the flags map them to bits in the architectural 'P' register as follows:

7  bit  0
---- ----
NV1B DIZC
|||| ||||
|||| |||+- Carry
|||| ||+-- Zero
|||| |+--- Interrupt Disable
|||| +---- Decimal
|||+------ (No CPU effect; see: the B flag)
||+------- (No CPU effect; always pushed as 1)
|+-------- Overflow
+--------- Negative

• The PHP (Push Processor Status) and PLP (Pull Processor Status) instructions can be used to retrieve or set this register directly via the stack.
• Interrupts, including the NMI and also the pseudo-interrupt BRK instruction, implicitly push the status register to the stack.
• Interrupts returning with RTI will implicitly pull the saved status register from the stack.
• The two bits with no CPU effect are ignored when pulling flags from the stack; there are no corresponding registers for them in the CPU.
• When P is displayed as a single 8-bit register by debuggers, there is no convention for what values to use for bits 5 and 4 and their values should not be considered meaningful.

C: Carry

---

• After ADC, this is the carry result of the addition.
• After SBC or CMP, this flag will be set if no borrow was the result, or alternatively a "greater than or equal" result.
• After a shift instruction (ASL, LSR, ROL, ROR), this contains the bit that was shifted out.
• Increment and decrement instructions do not affect the carry flag.
• Can be set or cleared directly with SEC, CLC.

Z: Zero

---

• After most instructions that have a value result, this flag will either be set or cleared based on whether or not that value is equal to zero.

I: Interrupt Disable

---

• When set, IRQ interrupts are inhibited. NMI, BRK, and reset are not affected.
• Can be set or cleared directly with SEI, CLI.
• Automatically set by the CPU when any interrupt is triggered (NMI, IRQ/BRK, or reset), and restored to its previous state when leaving an interrupt handler with RTI.
• If an IRQ is pending when this flag is cleared (i.e. the /IRQ line is low), an interrupt will be triggered immediately (RTI) or after a 1 instruction delay (CLI, PLP).

D: Decimal

---

• On the NES, decimal mode is disabled and so this flag has no effect. However, it still exists and can be observed and modified, as normal.
• On the original 6502, this flag causes some arithmetic instructions to use binary-coded decimal representation to make base 10 calculations easier.
• Can be set or cleared directly with SED, CLD.

V: Overflow

---

• ADC and SBC will set this flag if the signed result would be invalid, necessary for making signed comparisons.
• BIT will load bit 6 of the addressed value directly into the V flag.
• Can be cleared directly with CLV. There is no corresponding set instruction.

N: Negative

---

• After most instructions that have a value result, this flag will contain bit 7 of that result.
• BIT will load bit 7 of the addressed value directly into the N flag.

The B flag

---

While there are only six flags in the processor status register within the CPU, the value pushed to the stack contains additional state in bit 4 called the B flag that can be useful to software. The value of B depends on what caused the flags to be pushed. Note that this flag does not represent a register that can hold a value, but rather a transient signal in the CPU controlling whether it was processing an interrupt when the flags were pushed. B is 0 when pushed by interrupts (/IRQ and /NMI) and 1 when pushed by instructions (BRK and PHP).

Instruction	B	Side effects after pushing
/IRQ	0	I is set to 1
/NMI	0	I is set to 1
BRK	1	I is set to 1
PHP	1	None

The only way for an IRQ handler to distinguish /IRQ from BRK is to read the flags byte from the stack and test bit 4. The slowness of this is one reason why BRK wasn't used as a syscall mechanism. Instead, it was more often used to trigger a patching mechanism that hung off the /IRQ vector: a single byte in PROM, UVEPROM, flash, etc. would be forced to 0, and the IRQ handler would pick something to do instead based on the program counter.

Some debugging tools, such as Visual6502, display the B flag as bit 4 of P to save space on screen. The user can see it turn off at the start of an interrupt and back on after the CPU reads the vector.

External links

• koitsu's explanation