User:Ben Boldt: Difference between revisions
From NESdev Wiki
Jump to navigationJump to search
No edit summary |
No edit summary |
||
| Line 44: | Line 44: | ||
V R RAM chip connection | V R RAM chip connection | ||
* All pins have internal protection | * All pins have internal protection diodes from GND and to VCC/batt except pins 4 and 5. | ||
* Pins 4 and 5 measure infinite resistance to all other pins. | * Pins 4 and 5 measure infinite resistance to all other pins. | ||
* The 3 VCCs (8,9,12) are NOT internally connected to each other. | * The 3 VCCs (8,9,12) are NOT internally connected to each other. | ||
* GND pins (11,24,37,57) are internally connected to each other. | * GND pins (11,24,37,57) are internally connected to each other. | ||
* | * VCC/batt pins (10,25,38,56) are internally connected to each other. | ||
Revision as of 03:53, 9 January 2019
See my Wikipedia User Page.
MMC6 ASCII Pinout (sandbox/in progress):
___
/ \
/ \
(n) CPU A13 -> / 1 64 \ -> PRG A17 (r)
M2 -> / 2 63 \ <- CPU A14 (n)
(unknown) ?? / 3 O 62 \ -> PRG A18 (r)
n/c -- / 4 61 \ -> PRG A14 (r)
n/c -- / 5 60 \ -> PRG A15 (r)
(unknown) ?? / 6 59 \ -> PRG A13 (r)
(unknown) ?? / 7 58 \ <- CPU A12 (nr)
(VCC) ?? / 8 57 \ -- GND
(VCC) ?? / 9 56 \ -- VCC/batt
VCC/batt -- / 10 55 \ <- CPU A8 (nr)
GND -- / 11 ( ) 54 \ <- CPU A7 (nr)
(VCC) ?? / 12 53 \ <- CPU A9 (nr)
threshold -- / 13 52 \ <- CPU A6 (nr)
(n) PPU A10 -> / 14 51 \ <- CPU A5 (nr)
(n) PPU A11 -> / 15 50 \ -> PRG A16 (r) Orientation:
(unknown) ?? / 16 49 \ <- CPU A4 (nr) --------------------
/ Nintendo MMC6 \ 48 33
\ Package QFP-64, 0.8mm pitch / | |
(r) CHR A10 <- \ 17 48 / <- CPU A3 (nr) .------------.
(r) CHR A16 <- \ 18 47 / -> PRG /CE (r) 49-| |-32
(r) CHR A11 <- \ 19 46 / <- CPU A2 (nr) | Nintendo |
(n) PPU A12 -> \ 20 45 / <> CPU D7 (nr) |O MMC6B O|
(r) CHR A13 <- \ 21 ( ) 44 / <- CPU A1 (nr) | |
(r) CHR A12 <- \ 22 43 / <> CPU D6 (nr) 64-|o |-17
(r) CHR A14 <- \ 23 42 / <- CPU A0 (nr) \------------'
GND -- \ 24 41 / <> CPU D5 (nr) | |
VCC/batt -- \ 25 40 / <> CPU D0 (nr) 1 16
(r) CHR A15 <- \ 26 39 / <> CPU D4 (nr)
(n) CIRAM A10 <- \ 27 38 / -- VCC/batt Legend:
(nr) CHR /OE, PPU /RD -> \ 28 37 / -- GND ------------------------------
(nr) CHR /CE, PPU A13 -> \ 29 36 / <> CPU D1 (nr) --[MMC6]-- Power
(r) CHR A17 <- \ 30 35 / <> CPU D3 (nr) ->[MMC6]<- MMC6 input
(n) /IRQ <- \ 31 34 / <> CPU D2 (nr) <-[MMC6]-> MMC6 output
(n) /ROMSEL -> \ 32 33 / <- CPU R/W (n) <>[MMC6]<> Bidirectional
\ / ??[MMC6]?? Unknown
\ / n NES connection
\ / r ROM chip connection
V R RAM chip connection
- All pins have internal protection diodes from GND and to VCC/batt except pins 4 and 5.
- Pins 4 and 5 measure infinite resistance to all other pins.
- The 3 VCCs (8,9,12) are NOT internally connected to each other.
- GND pins (11,24,37,57) are internally connected to each other.
- VCC/batt pins (10,25,38,56) are internally connected to each other.
Battery Circuit:
+------|>|----/\/\/------+------|<|-----O NES 5V + | 1 kohm | --- 3V | ----- Lithium +--------------O MMC6 VCC/Batt | 2032 - | +---------------------------------------O NES GND, MMC6 GND
Threshold Circuit:
NES 5V O----/\/\/----+
181 ohm |
|
+-----O MMC6 Threshold
|
470 ohm |
NES GND, MMC6 GND O----/\/\/----+
NES-HKROM (Startropics 1) BOM:
R1 1 kohm R2 181 ohm R3 470 ohm C1 22uF 6.3V Electrolytic C2 10nF Ceramic C3 10nF Ceramic D1 Diode (0.6V Forward) D2 Diode (0.6V Forward) U1 PRG-ROM U2 CHR-ROM U3 CIC U4 MMC6 Batt 2032 3V Lithium
