Talk:VRC6: Difference between revisions

Revision as of 15:22, 23 October 2013

The VRC6 documentation (currently linked from here) seems to indicate that register $B003 has quite a lot more bits than we currently know about:

D0/D1: CHR/NT Bank mode
- mode 0 - normal
- mode 1 - regs 0-3 select 2KB CHR banks, regs 4-7 select nametable banks
- mode 2 - regs 0-3 select 1KB CHR banks at 0000-0FFF, regs 4-5 select 2KB CHR banks at 1000-1FFF, regs 6-7 select nametable banks (controlled by mirroring)
- mode 3 - pattern tables seemingly also get mapped into the nametables?
D2/D3: mirroring control
D4: 0 = Use extra 8KB CHR RAM for nametables (in bank modes 1-3); 1 = Use CHR ROM for nametables
D5: something related to CHR ROM?
D7: SRAM enable (1 = enable)

--Quietust (talk) 09:07, 23 October 2013 (MDT)

@@ Line 1: / Line 1: @@
 The VRC6 documentation (currently linked from [http://forums.nesdev.org/viewtopic.php?f=2&t=10611 here]) seems to indicate that register $B003 has quite a lot more bits than we currently know about:
-* D0/D1: VRAM/VRAM Back Mode
+* D0/D1: CHR/NT Bank mode
-* D2/D3: HV register
+** mode 0 - normal
-* D4: 0 = Use VRAM; 1 = Use VROM
+** mode 1 - regs 0-3 select 2KB CHR banks, regs 4-7 select nametable banks
+** mode 2 - regs 0-3 select 1KB CHR banks at 0000-0FFF, regs 4-5 select 2KB CHR banks at 1000-1FFF, regs 6-7 select nametable banks (controlled by mirroring)
+** mode 3 - pattern tables seemingly also get mapped into the nametables?
+* D2/D3: mirroring control
+* D4: 0 = Use extra 8KB CHR RAM for nametables (in bank modes 1-3); 1 = Use CHR ROM for nametables
 * D5: something related to CHR ROM?
 * D7: SRAM enable (1 = enable)
 --[[User:Quietust|Quietust]] ([[User talk:Quietust|talk]]) 09:07, 23 October 2013 (MDT)