Talk:NTSC video: Difference between revisions
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The part of the PPU that generates the video signal (immediately to the right of the NMI and CLK pins) appears to consist of a very long resistor between VCC and GND with taps at various points, and one of them (closest to VCC) is a switchable pulldown to GND (no doubt for color emphasis). The logic itself can select 12 different voltage levels (00/10/20/30, 0D/1D/2D/3D, synch, colorburst L/H, and GND), and they appear to correspond to 10 distinct voltage levels - one of the duplicates is at the highest voltage (likely 20/30), and the other one is the 3rd-lowest [non-GND] voltage (not sure which one). --[[User:Quietust|Quietust]] 17:59, 28 September 2011 (UTC) | The part of the PPU that generates the video signal (immediately to the right of the NMI and CLK pins) appears to consist of a very long resistor between VCC and GND with taps at various points, and one of them (closest to VCC) is a switchable pulldown to GND (no doubt for color emphasis). The logic itself can select 12 different voltage levels (00/10/20/30, 0D/1D/2D/3D, synch, colorburst L/H, and GND), and they appear to correspond to 10 distinct voltage levels - one of the duplicates is at the highest voltage (likely 20/30), and the other one is the 3rd-lowest [non-GND] voltage (not sure which one). --[[User:Quietust|Quietust]] 17:59, 28 September 2011 (UTC) | ||
*With the help of ChipSim, I've traced down exactly what the 12 voltage levels correspond to - Synch (GND), Colorburst L, Color 0D, Color xE/xF and Color 1D, Colorburst H, Color 2D, Color 00, Color 10, color 3D, Color 20 and Color 30 ("and" == two signals which select the same actual voltage). --[[User:Quietust|Quietust]] 11:17, 29 October 2012 (MDT) | *With the help of ChipSim, I've traced down exactly what the 12 voltage levels correspond to - Synch (GND), Colorburst L, Color 0D, Color xE/xF and Color 1D, Colorburst H, Color 2D, Color 00, Color 10, color 3D, Color 20 and Color 30 ("and" == two signals which select the same actual voltage). --[[User:Quietust|Quietust]] 11:17, 29 October 2012 (MDT) | ||
==Absolute Video Signal Timing== | |||
Some tests with Visual2C02 managed to confirm all of the contents of the Scanline Timing table, plus one more interesting bit of information: the ''offset''. Specifically, the "active" region begins at cycle '''4''', which is when the PPU is just finishing the attribute byte fetch for the 3rd tile in the scanline (the first 2 are fetched at the end of the previous scanline). --[[User:Quietust|Quietust]] 08:50, 1 November 2012 (MDT) | |||
Revision as of 14:50, 1 November 2012
The part of the PPU that generates the video signal (immediately to the right of the NMI and CLK pins) appears to consist of a very long resistor between VCC and GND with taps at various points, and one of them (closest to VCC) is a switchable pulldown to GND (no doubt for color emphasis). The logic itself can select 12 different voltage levels (00/10/20/30, 0D/1D/2D/3D, synch, colorburst L/H, and GND), and they appear to correspond to 10 distinct voltage levels - one of the duplicates is at the highest voltage (likely 20/30), and the other one is the 3rd-lowest [non-GND] voltage (not sure which one). --Quietust 17:59, 28 September 2011 (UTC)
- With the help of ChipSim, I've traced down exactly what the 12 voltage levels correspond to - Synch (GND), Colorburst L, Color 0D, Color xE/xF and Color 1D, Colorburst H, Color 2D, Color 00, Color 10, color 3D, Color 20 and Color 30 ("and" == two signals which select the same actual voltage). --Quietust 11:17, 29 October 2012 (MDT)
Absolute Video Signal Timing
Some tests with Visual2C02 managed to confirm all of the contents of the Scanline Timing table, plus one more interesting bit of information: the offset. Specifically, the "active" region begins at cycle 4, which is when the PPU is just finishing the attribute byte fetch for the 3rd tile in the scanline (the first 2 are fetched at the end of the previous scanline). --Quietust 08:50, 1 November 2012 (MDT)
