VRC6: Difference between revisions

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(→‎PPU Banking Style ($B003): additional note that bit 5 is normally set)
(→‎Mirroring: Oh! I misunderstood when I said vertical was forced, I mistakenly thought PPU A10 was passed, not the internal register LSB. Isn't it arbitrary then, not just vertical/1-screen?)
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When CIRAM is used (bit 4 clear), bit 5 should normally be set (override CIRAM A10) so that the replaced signal can be used to apply mirroring. Otherwise vertical or one-screen mirroring will be forced.
When CIRAM is used (bit 4 clear), bit 5 should normally be set (override CIRAM A10) so that the replaced signal can be used to apply mirroring. Otherwise the LSB of nametable banks will apply.


=== IRQ control ($F00x) ===
=== IRQ control ($F00x) ===

Revision as of 00:17, 11 March 2018

VRC6
Company Konami
Games 3 in NesCartDB
Complexity ASIC
Boards 351951, 351949A
PRG ROM capacity 256K
PRG ROM window 16K + 8K
PRG RAM capacity 8K
PRG RAM window 8K
CHR capacity 256K
CHR window 1K
Nametable mirroring H, V, or 1, switchable
Bus conflicts No
IRQ Yes
Audio Yes
iNES mappers 024, 026

The Konami's VRC6 ASIC mapper comes in two variants:

  • VRC6a - iNES Mapper 024 used for Akumajou Densetsu (Konami PCB 351951).
  • VRC6b - iNES Mapper 026 used for Madara and Esper Dream 2 (Konami PCB 351949A).

The difference between the two variants switches the A0 and A1 lines. The registers described on this page are for mapper 24, but for mapper 26 the register addresses must be adjusted ($x001 becomes $x002 and vice versa).

See VRC6 pinout for chip pinout.


Banks

  • CPU $8000-$BFFF: 16 KB switchable PRG ROM bank
  • CPU $C000-$DFFF: 8 KB switchable PRG ROM bank
  • CPU $E000-$FFFF: 8 KB PRG ROM bank, fixed to the last bank
  • CHR $0000-$03FF: 1 KB switchable CHR ROM bank
  • CHR $0400-$07FF: 1 KB switchable CHR ROM bank
  • CHR $0800-$0BFF: 1 KB switchable CHR ROM bank
  • CHR $0C00-$0FFF: 1 KB switchable CHR ROM bank
  • CHR $1000-$13FF: 1 KB switchable CHR ROM bank
  • CHR $1400-$17FF: 1 KB switchable CHR ROM bank
  • CHR $1800-$1BFF: 1 KB switchable CHR ROM bank
  • CHR $1C00-$1FFF: 1 KB switchable CHR ROM bank

Registers

Only address lines 0, 1, and 12-15 are used for registers, therefore mirrors can be found by ANDing the address with $F003 ($DE6A mirrors $D002)

The addresses described here are for mapper 24. The registers for mapper 26 can be found by swapping bits 0 and 1 of the address. 

    variant   lines     registers                       Mapper Number
    =================================================================
    VRC6a:    A0, A1    $x000, $x001, $x002, $x003      024
    VRC6b:    A1, A0    $x000, $x002, $x001, $x003      026

16k PRG Select ($8000-$8003)

7  bit  0
---------
.... PPPP
     ||||
     ++++- Select 16 KB PRG ROM at $8000

8k PRG Select ($C000-$C003)

7  bit  0
---------
...P PPPP
   | ||||
   +-++++- Select 8 KB PRG ROM at $C000

PPU Banking Style ($B003)

7  bit  0
---------
W.PN MMDD
| || ||||
| || ||++- PPU banking mode; see below
| || ++--- Mirroring varies by banking mode, see below
| |+------ 1: Nametables come from CHRROM, 0: Nametables come from CIRAM
| +------- CHR A10 is 1: subject to further rules 0: according to the latched value
+--------- PRG RAM enable

The VRC6 supports the use of a larger RAM to provide more nametables. However, the three commercial VRC6 games neither provided extra nametable RAM, nor used ROM nametables. As a result these games only ever write the values $20, $24, $28, $2C, $A0, $A4, $A8, and $AC to this register.

CIRAM A10 is always connected to CHR A10, and bit 5 affects the behaviour of this signal (see below for details). The commercial games always left this bit set.

CHR Select 0…7 ($Dxxx, $Exxx)

For brevity, we refer to the registers at $D000 through $D003 and $E000 through $E003 as R0 through R7.

The lower 3 bits of the $B003 register affect where the registers are used:

[$B003] & $03 → 0 1 2 or 3
CHR bank Register used
$0000-$03FF R0 R0 R0
$0400-$07FF R1 R1
$0800-$0BFF R2 R1 R2
$0C00-$0FFF R3 R3
$1000-$13FF R4 R2 R4
$1400-$17FF R5
$1800-$1BFF R6 R3 R5
$1C00-$1FFF R7
[$B003] & $07 → 0, 6, or 7 1 or 5 2, 3, or 4
Nametable bank Register used
$2000-$23FF R6 R4 R6
$2400-$27FF R6 R5 R7
$2800-$2BFF R7 R6 R6
$2C00-$2FFF R7 R7 R7

When bit 5 of $B003 is set, 2 KiB banks pass PPU A10 through (ignoring the LSB of the register).

When bit 5 of $B003 is clear, CHR A10 will be controlled directly by the register LSB, causing 2 KiB banks to have duplicate 1 KiB halves. Existing Konami games did not use this configuration.

Mirroring

For the nametables, if bit 5 of $B003 is set and the lower 4 bits of $B003 have one of the following values, CHR/CIRAM A10 is replaced:

[$B003] & $0F CHR A10
0 or 7 PPU A10 ("vertical mirroring")
4 or 3 PPU A11 ("horizontal mirroring")
8 or F Ground ("one screen A")
C or B Vcc ("one screen B")
all other values use "Nametable bank" table above

When CIRAM is used (bit 4 clear), bit 5 should normally be set (override CIRAM A10) so that the replaced signal can be used to apply mirroring. Otherwise the LSB of nametable banks will apply.

IRQ control ($F00x)

For details on IRQ operation, see VRC IRQs. Many VRC mappers use the same IRQ system.

The VRC6 IRQ can be used to count either CPU cycles, or scanlines as a multiple of CPU cycles. 

       7  bit  0
       ---------
$F000: LLLL LLLL - IRQ Latch
$F001: .... .MEA - IRQ Control
$F002: .... .... - IRQ Acknowledge
  • L - reload value for latch
  • M - mode (1=cycle, 0=scanline)
  • E - enable IRQ
  • A - acknowledge bit

Sound ($900x, $A00x, $B000-$B002)

For details on sound information, see VRC6 audio.

References

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