UNIF/UNL-DripGame

UNL-DripGame is a ASIC (actually, FPGA) mapper invented by Quietust for a single game.

The iNES number is #4098. The UNIF name is "UNL-DripGame".

Memory map

CPU:

• $4800-$5FFF = Readable registers
• $6000-$7FFF = PRG RAM
• $8000-$BFFF = Switchable bank
• $C000-$FFFF = Fixed to the last bank

Readable registers

$4800-$4FFF (Status)

[DSSS SSSS]
 |||| ||||
 |+++-++++---- Ready flag; $64 if ready
 +------------ Switch

All other registers should not be touched until it is ready.

$5000-$57FF (Sound channel 0 status)

[FE.. ....]
 ||
 |+----------- Buffer is empty
 +------------ Buffer is full

$5800-$5FFF (Sound channel 1 status)

Similar to $5000 but for the second channel.

Writable registers

All of these registers are mirrored at $8000-$BFFF; the low four bits select the register number.

$8000 (Sound channel 0 silence register)

Writing anything silences channel 0 and clears the buffer.

$8001 (Sound channel 0 data)

Writing data inserts it into the buffer.

$8002 (Sound channel 0 low period)

[PPPP PPPP]

Specify low 8-bits of period of channel 0.

$8003 (Sound channel 0 high period)

[VVVV PPPP]
 |||| ||||
 |||| ++++---- High 4-bits of period
 ++++--------- Volume control

Specify high 4-bits of period of channel 0, and volume control.

$8004 (Sound channel 1 silence register)

Writing anything silences channel 1 and clears the buffer.

$8005 (Sound channel 1 data)

Writing data inserts it into the buffer.

$8006 (Sound channel 1 low period)

[PPPP PPPP]

Specify low 8-bits of period of channel 1.

$8007 (Sound channel 1 high period)

[VVVV PPPP]
 |||| ||||
 |||| ++++---- High 4-bits of period
 ++++--------- Volume control

Specify high 4-bits of period of channel 1, and volume control.

$8088 (Low IRQ register)

[XXXX XXXX]
 |||| ||||
 ++++-++++---- Low 8-bits of IRQ value

$8089 (High IRQ register)

[EXXX XXXX]
 |||| ||||
 |+++-++++---- High 7-bits of IRQ value
 +------------ Enable flag

IRQ is automatically disabled when it is overflow. This register also is used for acknowledging the interrupt.

$808A (Control)

[.... SAMM]
      ||||
      ||++---- Nametable mirroring (00=V, 01=H, 10=1sc-A, 11=1sc-B)
      |+------ Enable extended attribute table
      +------- Enable writing to SRAM

$808B (PRG bank)

[.... PPPP]
      ||||
      ++++---- Select 16K PRG bank at $8000-$BFFF

$808C (CHR bank 0)

[.... CCCC]
      ||||
      ++++---- Select 2K CHR bank at $0000-$07FF

$808D (CHR bank 1)

[.... CCCC]
      ||||
      ++++---- Select 2K CHR bank at $0800-$0FFF

$808E (CHR bank 2)

[.... CCCC]
      ||||
      ++++---- Select 2K CHR bank at $1000-$17FF

$808F (CHR bank 3)

[.... CCCC]
      ||||
      ++++---- Select 2K CHR bank at $1800-$1FFF

Extended attribute tables

This memory is write-only and is mapped at $C000-$C3FF for first nametable, and $C400-$C7FF for last nametable. It is mirrored across $C000-$FFFF.

Only low 2-bits of data are used, and is used for deciding the color of the corresponding tile position in a nametable.

IRQ

Data written to low IRQ register is stored in a buffer but won't reload the counter until the high IRQ register is programmed.

IRQ is count down per cycle, and then trigger the IRQ and stop the timer when it expires.

Audio

There are two channels, both of which function in the same way.

The buffers are "first in first out" buffers which store unsigned sample data with $80 meaning no signal.

Each buffer stores 256 bytes which can be written in sequence. If a channel is inactive, filling the buffer with even one byte activates that channel immediately.

Changes to the period are delayed until the sample is finished playing.

The channel becomes inactive as soon as the buffer becomes empty.