SxROM: Difference between revisions

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m (→‎Various notes: oops it was mapper 001 not mapper 1)
(exchanged the info about SXROM etc... it makes sense to have it sumarized here and detailed in the MMC1 article)
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== Higher CHR lines ==
== Higher CHR lines ==


Some boards with CHR RAM, which doesn't uses the higher CHR lines, have re-routed those lines for a different usage :
The SUROM, SOROM, and SXROM boards are extensions of SNROM, which has CHR RAM and PRG RAM.
Because CHR RAM doesn't need bankswitching, these boards use the CHR bank select lines to switch different things:
*SUROM uses the upper CHR bank select line coming out of the mapper to control the upper address line of its 512KB PRG ROM.
*SOROM uses a similar method, using the second-highest CHR bank select line to choose between two 8KB PRG RAM chips.
*SXROM is a combination of SOROM and SUROM, addressing both 512KB of PRG ROM and 32KB of PRG RAM.


=== SNROM ===
In these scenarios, however, both CHR bank registers must be set to the same value (or the CHR bank size must be set to 8KB), or the PRG ROM/RAM will be bankswitched as the PPU renders, causing disastrous results.
 
==== CHR bank 0 (internal, $A000-$BFFF) ====
4bit0
-----
ExxxC
|  |
|  +- Select 4 KB CHR RAM bank at PPU $0000 (ignored in 8 KB mode)
+----- PRG RAM disable (0: enable, 1: open bus)
 
==== CHR bank 1 (internal, $C000-$DFFF) ====
4bit0
-----
ExxxC
|  |
|  +- Select 4 KB CHR RAM bank at PPU $1000 (ignored in 8 KB mode)
+----- PRG RAM disable (0: enable, 1: open bus) (ignored in 8 KB mode)
 
Both the <code>E</code> bit and the <code>R</code> bit (in standard MMC1 registers) should be clear in order for the PRG RAM to be writable or readable. This bit is more "reliable" on authentic hardware as it is implemented even in older boards with older MMC1's, while the 'R' bit was only introduced later.
But because the <code>E</code> bit wasn't absolutely confirmed by the homebrew community until October 2010,[http://nesdev.parodius.com/bbs/viewtopic.php?t=7045] emulators tend not to implement it.
 
=== SOROM, SUROM and SXROM ===
 
==== CHR bank 0 (internal, $A000-$BFFF) ====
4bit0
-----
PSSxC
||| |
||| +- Select 4 KB CHR RAM bank at PPU $0000 (ignored in 8 KB mode)
|++--- Select 8 KB PRG RAM bank
+----- Select 256 KB PRG ROM bank
 
==== CHR bank 1 (internal, $C000-$DFFF) ====
4bit0
-----
PSSxC
||| |
||| +- Select 4 KB CHR RAM bank at PPU $1000 (ignored in 8 KB mode)
|++--- Select 8 KB PRG RAM bank (ignored in 8 KB mode)
+----- Select 256 KB PRG ROM bank (ignored in 8 KB mode)
 
The SOROM board only implement the upper <code>S</code> bit, while the SUROM board only implements the <code>P</code> bit.
 
In 4KB CHR bank mode, the <code>P</code>, <code>S</code> and <code>E</code> bits in both CHR bank registers must be set to the same values, or the PRG ROM and/or RAM will be bankswitched/enabled as the PPU renders, in a similar fashion as [[MMC3#Hardware|MMC3]]'s scanline counter. As there is not much of a reason to use 4 KB bankswitching with CHR RAM, it is wise for programs to just set 8 KB bankswitching mode in the [[MMC1#Control (internal, $8000-$9FFF)|Control register]].


== Various notes ==
== Various notes ==

Revision as of 17:53, 14 November 2010

The generic designation SxROM refers to cartridge boards made by Nintendo that use the Nintendo MMC1 mapper.

The following SxROM boards are known to exist:

Board PRG ROM PRG RAM CHR
SAROM 64 KB 8 KB 16,32,64 KB ROM
SBROM 64 KB 16,32,64 KB ROM
SCROM 64 KB 128 KB ROM
SEROM 32 KB 16,32,64 KB ROM
SFROM 128,256 KB 16,32,64 KB ROM
SGROM 128,256 KB 8 KB RAM
SHROM 32 KB 128 KB ROM
SJROM 128,256 KB 8 KB 16,32,64 KB ROM
SKROM 128,256 KB 8 KB 128 KB ROM
SLROM 128,256 KB 128 KB ROM
SL1ROM 64,128,256 KB 128 KB ROM
SL2ROM
SL3ROM
SLRROM
SMROM 256 KB 8 KB RAM
SNROM 128,256 KB 8 KB 8 KB RAM
SOROM 128,256 KB 16 KB 8 KB RAM
SUROM 512 KB 8 KB 8 KB RAM
SXROM 128,256,512 KB 32 KB 8 KB RAM


Solder pad config

Battery data retention (SAROM, SJROM, SKROM, SNROM, SUROM, SXROM only)

  • PRG RAM retaining data : 'SL' disconnected, Battery, D1, D2, R1 R2 and R3 present.
  • PRG RAM not retaining data : 'SL' connected, leave slots for Battery, D1, D2, R1, R2 and R3 free.

Even if the SOROM boards utilizes a battery, it is connected to only one PRG RAM chip. The first RAM chip will not retain its data, but the second one will.

Higher CHR lines

The SUROM, SOROM, and SXROM boards are extensions of SNROM, which has CHR RAM and PRG RAM. Because CHR RAM doesn't need bankswitching, these boards use the CHR bank select lines to switch different things:

  • SUROM uses the upper CHR bank select line coming out of the mapper to control the upper address line of its 512KB PRG ROM.
  • SOROM uses a similar method, using the second-highest CHR bank select line to choose between two 8KB PRG RAM chips.
  • SXROM is a combination of SOROM and SUROM, addressing both 512KB of PRG ROM and 32KB of PRG RAM.

In these scenarios, however, both CHR bank registers must be set to the same value (or the CHR bank size must be set to 8KB), or the PRG ROM/RAM will be bankswitched as the PPU renders, causing disastrous results.

Various notes

  • SLxROM boards are functionally identical to SLROM, but with different chip pinouts. Some of them have an additional 74HC32 chip to combine PPU /RD and PPU /A13 into a single enable signal for the CHR-ROM chip that has only 28 pins.
  • SMROM is functionally identical to SGROM, but features two 128 KB PRG ROM chips instead of one 256 KB. Only a very early MMC1 game in japan is known to have used this board, and it is the only known Nintendo-made board which combines smaller ROM chips to get a bigger ROM.
  • Even boards which different usage of upper CHR lines are all assigned to INES Mapper 001. Emulators can distinguish SOROM and SXROM from SNROM using the new PRG RAM size fields in NES 2.0 or using a PRG hash for legacy iNES ROMs. Therefore, it is recommended that ROM images of SOROM and SXROM games be stored in NES 2.0 format to allow an emulator to distinguish them from SNROM or SUROM.
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