PPU: Difference between revisions

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(I don't know what else the PPU could possibly render other than data; I think this word is just fluff)
 
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The NES PPU, or Picture Processing Unit, generates a composite video signal with 240 lines of pixels, designed to be received by a television. When the Famicom chipset was designed in the early 1980s, it was considered quite an advanced 2D picture generator for video games.  
The NES PPU, or Picture Processing Unit, generates a composite video signal with 240 lines of pixels, designed to be received by a television. When the Famicom chipset was designed in the early 1980s, it was considered quite an advanced 2D picture generator for video games.  


It has its own address space, which typically contains 10 kilobytes of memory: 8 kilobytes of ROM or RAM on the Game Pak (possibly more with one of the common Mappers) to store the shapes of background and sprite tiles, plus 2 kilobytes of RAM in the console to store a map or two. Two separate, smaller address spaces hold a palette, which controls which colors are associated to various indices, and OAM (Object Attribute Memory), which stores the position, orientation, shape, and color of the sprites, or independent moving objects. These are internal to the PPU itself and use dynamic memory (which will slowly decay if the PPU is not rendering data).
It has its own address space, which typically contains 10 kilobytes of memory: 8 kilobytes of ROM or RAM on the Game Pak (possibly more with one of the common [[mapper]]s) to store the shapes of background and sprite tiles, plus 2 kilobytes of RAM in the console to store a map or two. Two separate, smaller address spaces hold a palette, which controls which colors are associated to various indices, and OAM (Object Attribute Memory), which stores the position, orientation, shape, and color of the sprites, or independent moving objects. These are internal to the PPU itself, and while the palette is made of static memory, OAM uses dynamic memory (which will slowly decay if the PPU is not rendering).
<noinclude>


=== Programmer's reference ===
=== Programmer's reference ([[PPU_programmer_reference|printer friendly]]) ===  
* [[PPU_registers|Registers]]
* [[PPU_registers|Registers]]
* [[PPU_pattern_tables|Pattern tables]]
* [[PPU_pattern_tables|Pattern tables]] (tile graphics for background and sprites)
* [[PPU_OAM|OAM]]
* Background graphics
* [[PPU_nametables|Nametables]]
** [[PPU_nametables|Nametables]]
* [[PPU_attribute_tables|Attribute tables]]
** [[PPU_attribute_tables|Attribute tables]]
* [[PPU_OAM|OAM]] (sprites)
* [[PPU_palettes|Palettes]]
* [[PPU_palettes|Palettes]]
 
* [[PPU_memory_map|Memory map]]


=== Hardware behaviors ===
=== Hardware behaviors ===
* [[PPU_ntsc_pal_difference|NTSC/PAL differences]]
* [[PPU_frame_timing|Frame timing]]
* [[PPU_power_up_state|Power up state]]
* [[PPU_power_up_state|Power up state]]
* [[NMI]]
* [[Cycle reference chart#Clock_rates|Clock rate]] and other NTSC/PAL/Dendy differences
* [[NTSC video]]
* [[PPU scrolling|Scrolling]]
* [[PPU_rendering|Rendering]]
* [[PPU_sprite_evaluation|Sprite evaluation]]
* [[PPU_sprite_priority|Sprite priority]]
* [[Overscan]]
* [[PPU_pin_out_and_signal_description|PPU pinout and signals]]
* [[:File:Ppu.svg|NTSC PPU frame timing diagram]]
* [[Visual 2C02]]: A hardware-level PPU simulator
* [[PPU variants|List of known PPU versions and variants]]
=== Notes ===
* The [[NTSC video]] signal is made up of 262 scanlines, and 20 of those are spent in vblank state. After the program has received an NMI, it has about 2270 cycles to update the palette, sprites, and nametables as necessary before rendering begins.
* On NTSC systems, the PPU divides the master clock by 4 while the CPU uses the master clock divided by 12. Since both clocks are fed off the same master clock, this means that there are '''exactly''' three PPU ticks per CPU cycle, with no drifting over time (though the clock alignment might vary depending on when you press the Reset button).
* On PAL systems, the PPU divides the master clock by 5 while the CPU uses the master clock divided by 16. As a result, there are exactly 3.2 PPU ticks per CPU cycle.


</noinclude>
=== See also ===


=== Notes ===
* [http://nesdev.org/2C02%20technical%20reference.TXT 2C02 technical reference] by Brad Taylor. (Pretty old at this point; information on the wiki might be more up-to-date.)
* The NTSC video signal is made up of 262 scanlines, and 20 of those are spent in vblank state. After the program has received an NMI, it has about 2270 cycles to update the palette, sprites, and nametables as necessary before rendering begins.
<noinclude>
* A printer friendly version covering all section is available [[PPU_ALL|here]].
</noinclude>

Latest revision as of 05:01, 14 February 2023

The NES PPU, or Picture Processing Unit, generates a composite video signal with 240 lines of pixels, designed to be received by a television. When the Famicom chipset was designed in the early 1980s, it was considered quite an advanced 2D picture generator for video games.

It has its own address space, which typically contains 10 kilobytes of memory: 8 kilobytes of ROM or RAM on the Game Pak (possibly more with one of the common mappers) to store the shapes of background and sprite tiles, plus 2 kilobytes of RAM in the console to store a map or two. Two separate, smaller address spaces hold a palette, which controls which colors are associated to various indices, and OAM (Object Attribute Memory), which stores the position, orientation, shape, and color of the sprites, or independent moving objects. These are internal to the PPU itself, and while the palette is made of static memory, OAM uses dynamic memory (which will slowly decay if the PPU is not rendering).

Programmer's reference (printer friendly)

Hardware behaviors

Notes

  • The NTSC video signal is made up of 262 scanlines, and 20 of those are spent in vblank state. After the program has received an NMI, it has about 2270 cycles to update the palette, sprites, and nametables as necessary before rendering begins.
  • On NTSC systems, the PPU divides the master clock by 4 while the CPU uses the master clock divided by 12. Since both clocks are fed off the same master clock, this means that there are exactly three PPU ticks per CPU cycle, with no drifting over time (though the clock alignment might vary depending on when you press the Reset button).
  • On PAL systems, the PPU divides the master clock by 5 while the CPU uses the master clock divided by 16. As a result, there are exactly 3.2 PPU ticks per CPU cycle.

See also

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