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| [[Category:APU]] | | #REDIRECT [[APU#Status ($4015)]] |
| The [[APU|NES APU]] status register allows channels to be enabled and disabled, and the current playing status of channels and the interrupt flags to be read.
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| {| border=1
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| | '''$4015''' || <tt>---D.NT21</tt> || '''NES APU Status''' (write)
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| |-
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| | bit 4 || <tt>---D ----</tt> || If clear, the [[APU DMC|DMC's bytes remaining]] is set to 0, otherwise the DMC sample is restarted ''only if'' the DMC's bytes remaining is 0.
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| |-
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| | bit 3 || <tt>---- N---</tt> || [[APU Noise|Noise channel]]'s [[APU Length Counter|length counter enabled flag]]
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| |-
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| | bit 2 || <tt>---- -T--</tt> || [[APU Triangle|Triangle channel]]'s [[APU Length Counter|length counter enabled flag]]
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| |-
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| | bit 1 || <tt>---- --2-</tt> || [[APU Pulse|Pulse channel 2]]'s [[APU Length Counter|length counter enabled flag]]
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| |-
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| | bit 0 || <tt>---- ---1</tt> || [[APU Pulse|Pulse channel 1]]'s [[APU Length Counter|length counter enabled flag]]
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| |-
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| |colspan=2| Side effects || After the write, the [[APU DMC|DMC's interrupt flag]] is cleared, any length counter that is disabled is reset to 0.
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| |colspan=3|
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| | '''$4015''' || <tt>IF-D.NT21</tt> || '''NES APU Status''' (read)
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| |-
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| | bit 7 || <tt>I--- ----</tt> || [[APU DMC|DMC interrupt]] flag
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| |-
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| | bit 6 || <tt>-F-- ----</tt> || [[APU Frame Counter|Frame interrupt]] flag
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| |-
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| | bit 4 || <tt>---D ----</tt> || [[APU DMC|DMC bytes remaining]] is non-zero
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| |-
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| | bit 3 || <tt>---- N---</tt> || [[APU Noise|Noise channel]]'s [[APU Length Counter|length counter]] is non-zero
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| |-
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| | bit 2 || <tt>---- -T--</tt> || [[APU Triangle|Triangle channel]]'s [[APU Length Counter|length counter]] is non-zero
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| |-
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| | bit 1 || <tt>---- --2-</tt> || [[APU Pulse|Pulse channel 2]]'s [[APU Length Counter|length counter]] is non-zero
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| |-
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| | bit 0 || <tt>---- ---1</tt> || [[APU Pulse|Pulse channel 1]]'s [[APU Length Counter|length counter]] is non-zero
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| |-
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| |colspan=2| Side effects || Clears the [[APU Frame Counter|frame interrupt]] flag after being read (but ''not'' the [[APU DMC|DMC]] interrupt flag).<br>If an interrupt flag was set at the same moment of the read, it will read back as 1 but it will ''not'' be cleared.
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| |}
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