INES Mapper 176: Difference between revisions

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(Add FS006 board, which is like FS005 but only with optional 8 KiB of WRAM. Clarify that the RAM Configuration Register only exists on the Waixing variants.)
 
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{{DEFAULTSORT:176}}[[Category:iNES Mappers]][[Category:Multicart mappers]][[Category:MMC3-like mappers]][[Category:MMC3 with CHR ROM and CHR RAM]][[Category:Mappers with scanline IRQs]][[Category:Mappers with large PRG RAM]]
{{DEFAULTSORT:176}}[[Category:iNES Mappers]][[Category:Multicart mappers]][[Category:MMC3-like mappers]][[Category:MMC3 with CHR ROM and CHR RAM]][[Category:Mappers with scanline IRQs]][[Category:Mappers with large PRG RAM]][[Category:NES 2.0 mappers with submappers]]
iNES Mapper 176 is used by many multicarts as well as mid-2000s' new releases and re-releases from Waixing. It consists of an [[MMC3]] clone with greatly extended capabilities.
'''iNES Mapper 176''' denotes the '''8025''' enhanced [[MMC3]] chipset. It used by many multicarts, Chinese single-game and educational computer cartridges, and Techno Source's ''Intellivision X2'' Plug-and-Play console. Incompatible variations exist that are denoted via NES 2.0 Submapper.
Its UNIF board names are:
* '''BMC-FK23C''' (no WRAM, no DIP switch)
* '''BMC-FK23CA''' (no WRAM, with DIP switch)
* '''BMC-Super24in1SC03''' (functional duplicate of '''BMC-FK23C''')
* '''WAIXING-FS005''' (alternative name: Bensheng BS-001) (32 KiB battery-backed WRAM, 8 KiB of CHR-RAM, no DIP switch)
* '''WAIXING-FS006''' (optional 8 KiB battery-backed WRAM, optional 8 KiB of CHR-RAM, no DIP switch)
 
Three incompatible subtypes exist that do not correspond to these UNIF board names. No submappers have been proposed, as the subtypes can be easily discerned heuristically by looking at ROM sizes:
* '''Subtype 0''', ROM size other than specified below: boot with Extended MMC3 mode disabled (boots in first 512 KiB of PRG-ROM regardless of ROM size)
* '''Subtype 1''', 1024 KiB PRG-ROM, 1024 KiB CHR-ROM: boot with Extended MMC3 mode enabled (boots in last 512 KiB of the first 2 MiB of PRG-ROM)
* '''Subtype 2''', 16384 KiB PRG-ROM, no CHR-ROM: Like '''Subtype 0''', but MMC3 registers $46 and $47 swapped, as on the [[RAMBO-1]].


{| class="wikitable"
! colspan="13" | Submappers
|-
! rowspan="2" | # !! rowspan="2" | PCB codes !! rowspan="2" | [[UNIF]] MAPR !! colspan="5" | MMC3 !! colspan="4" | Outer bank registers !! rowspan="2" | Example
|-
! Ext. mode !! PRG bits !! $46/47 !! [[Mirroring#Single-Screen|1SM]] !! Extra WRAM !! Address mask !! PRG A21+ !! CHR A21+ !! CNROM latch
|-
| 0 || LP-8002KB, SFC-12B || '''BMC-Super24in1SC03'''  || - || 6 || normal || - || - || $Fxx3 || - || - || - || ''YH-xxx'' multicarts, ''Rockman 6-in-1''
|-
| 1 || FK-xxx/BS-xxx || '''BMC-FK23C'''/'''BMC-FK23CA''' || $5FF3.1 || 8 || normal || - || - || $Fxx3 || - || - || yes || ''FK-xxxx'' multicarts
|-
| 2 || FS005/FS006 || '''WAIXING-FS005''' || $5FF3.1 || 6 || swapped || yes || $A001.0-1 || $Fxx3 || $5xx0.3/7, $5xx2.6-7/5 || - || - || Waixing 2005+ re-releases, ''245-in-1 Real Game''
|-
| 3 || JX9003B || - || - || 8 || normal || - || - || $Fxx7 || $5xx5 || $5xx6 || - || ''Super Mario 160-in-1 Funny Time''
|-
| 4 || ? || - || - || 6 || normal || - || - || $Fxx3 || $5xx2.7 || - || - || ''GameStar Smart Genius Deluxe''
|-
| 5 || HST-162|| - || - || 6 || normal || - || - || $Fxx3 || $4800 || - || - || ''Game 500-in-1''
|-
|}
* The '''SFC-12B''' PCB (submapper 0) mounts both CHR-ROM and CHR-RAM that are selected via $5xx0.5.
* Eight MMC3 PRG bits mean that bit 6 and 7 of $8000.6/7 are applied, and the fixed banks are $FE/$FF rather than $3E/$3F. This implies that the multicart's reset vector lies at address PRG-ROM address $1FFFFC rather than $7FFFC if the PRG-ROM is that large.
=Registers=
=Registers=
Registers in the $5000-$5FFF range can be temporarily disabled through the [[#RAM Configuration Register ($A001)|RAM Configuration Register ($A001)]].
'''FS005 (Submapper 2)''' can disable the registers in the $5000-$5FFF range using the [[#RAM Configuration Register ($A001)|RAM Configuration Register ($A001)]]. The same register also enables a mixed CHR-ROM/CHR-RAM mode that is similar to [[INES Mapper 195]].


==Mode Register ($5xx0)==
==Mode Register ($5xx0)==
Mask: $5''xx''3, ''x'' determined by [[#DIP Switch|DIP Switch setting]]
Mask: $F''xx''7 ('''Submapper 3'''), $5''xx''3 (all others), ''x'' determined by [[#Solder Pad|solder pad setting]]
 
  7654 3210
  7654 3210
  ---- ----
  ---- ----
Line 24: Line 34:
  |||| ||||
  |||| ||||
  |||| |+++- Select PRG Banking Mode (ignored in Extended MMC3 Mode)
  |||| |+++- Select PRG Banking Mode (ignored in Extended MMC3 Mode)
  |||| |      0: MMC3 PRG Mode, 512 KiB Outer PRG Bank Size
  |||| |      0: MMC3 PRG Mode, 2 MiB/512 KiB Outer PRG Bank Size
  |||| |      1: MMC3 PRG Mode, 256 KiB Outer PRG Bank Size
  |||| |      1: MMC3 PRG Mode, 256 KiB Outer PRG Bank Size
  |||| |      2: MMC3 PRG Mode, 128 KiB Outer PRG Bank Size
  |||| |      2: MMC3 PRG Mode, 128 KiB Outer PRG Bank Size
  |||| |      3: NROM-128 PRG Mode, 16 KiB PRG at $8000-$BFFF mirrored at $C000-$FFFF
  |||| |      3: NROM-128 PRG Mode, 16 KiB PRG at $8000-$BFFF mirrored at $C000-$FFFF
  |||| |      4: NROM-256 PRG Mode, 32 KiB PRG at $8000-$FFFF
  |||| |      4: NROM-256 PRG Mode, 32 KiB PRG at $8000-$FFFF
  |||| |      5-7: Never used
  |||| |      5: UNROM PRG Mode, 16 KiB PRG at $8000-$BFFF, inner bank #7 at $C000-$FFFF
  |||| +---- 16 KiB PRG Base bit 7
|||| |      6-7: Never used
  |||| +---- PRG A21 ('''Submapper 2''' only)
  |||+------ Select Outer CHR Bank Size
  |||+------ Select Outer CHR Bank Size
  |||        0: In MMC3 CHR Mode: 256 KiB
  |||        0: In MMC3 CHR Mode: 256 KiB
  |||            In CNROM CHR Mode: 32 KiB
  |||            In CNROM CHR Mode: 32 KiB ('''Submapper 1''' only)
  |||        1: In MMC3 CHR Mode: Same as Outer PRG Bank Size
  |||        1: In MMC3 CHR Mode: 128 KiB
  |||            In CNROM CHR Mode: 16 KiB
  |||            In CNROM CHR Mode: 16 KiB ('''Submapper 1''' only)
  ||+------- Select CHR Memory Type
  ||+------- '''Submappers 0/1''' with both CHR-ROM and CHR-RAM (e.g. '''SFC-12B''' PCB):
  ||          0: CHR-ROM
  ||          0: Select CHR-ROM
  ||          1: CHR-RAM
  ||          1: Select CHR-RAM
  |+-------- CHR Mode
||        '''Submapper 1''' with $5xx0.6=1:
  |          0: MMC3 CHR Mode
||          0: Enable CNROM latch (CNROM mode)
  |          1: NROM/CNROM CHR Mode
||          1: Disable CNROM latch (NROM mode)
  +--------- 16 KiB PRG Base bit 8
  |+-------- CHR A10-12 Mode
  |          0: from MMC3
  |          1: from PPU
  +--------- PRG A22 ('''Submapper 2''' only)
   
   
  Power-on value: $00
  Power-on value: $00
* It is possible to use NROM mode for PRG banking and MMC3 mode for CHR banking.
* NROM versus CNROM CHR Mode is decided in the Extended Mode Register ($5xx3).
* Bit 5 applies to CHR Memory in its entirety, while Bit 2 of the [[#RAM Configuration Register ($A001)|RAM Configuration Register ($A001)]] selects mixed CHR-ROM/RAM mode.
* The inner and outer bank numbers are combined ...
** ... in MMC3 PRG/CHR modes: by masking the MMC3 bank register content according to the specified size (128 or 256 KiB) and OR'ing with the opposite-masked content of the PRG ($5xx1)/CHR ($5xx2) Base;
** ... in NROM PRG/CHR mode: by using the PRG ($5xx1)/CHR Base ($5xx2) directly.
** ... in CNROM CHR mode: by masking the CNROM Latch according to the selected Outer CHR Bank Size, and OR'ing with the ''unmasked'' content of the CHR Base ($5xx2);
** ... in [[#Extended Mode Register ($5xx3)|Extended MMC3 mode]] by OR'ing the ''unmasked'' (extended) bank register content with the ''unmasked'' content of the PRG ($5xx1)/CHR ($5xx2) Base.
==PRG Base Register ($5xx1)==
Mask: $5''xx''3, ''x'' determined by [[#DIP Switch|DIP Switch setting]]


==PRG Base Register LSB ($5xx1)==
Mask: $F''xx''7 ('''Submapper 3'''), $F''xx''3 (all others), ''x'' determined by [[#Solder Pad|solder pad setting]]
  7654 3210
  7654 3210
  ---- ----
  ---- ----
  .PPP PPPP
  .PPP PPPP
   ||| ||||
   ||| ||||
   +++-++++- 16 KiB PRG Base bits 0-6
   +++-++++- PRG A20..A14
Power-on value: $00
Depending on the PRG banking mode set via $5xx0, only the higher bits of this register are applied:
PRG A..
21111111
09876543
--------
MMMMMMMM  Submappers 1/3 in PRG Mode 0 (MMC3 2 MiB) or Extended MMC3 Mode
BBMMMMMM  Submappers 0/2/4 in PRG Mode 0 (MMC3 512 KiB)
BBBMMMMM  PRG Mode 1 (MMC3 256 KiB)
BBBBMMMM  PRG Mode 2 (MMC3 128 KiB)
BBBBBBBC  PRG Mode 3 (NROM-128)
BBBBBBCC  PRG Mode 4 (NROM-256)
BBBBLLLC  PRG Mode 5 (UNROM)
M: Bit comes from MMC3 ($8000.6/7 or fixed bank)
B: Bit comes from PRG Base Register ($5xx1)
L: Bit comes from UNROM Latch ($8000-$FFFF or fixed bank)
C: Bit comes from CPU
 
'''Submapper 5''' only selects PRG A14-A18 (i.e. 512 KiB) via this register, selecting upper PRG bits via register [[#PRG Base Register MSB ($4800), Submapper 5 only|$4800]].
==PRG Base Register MSB ($5xx5), Submapper 3 only==
Mask: $F''xx''7 ('''Submapper 3'''), ''x'' determined by [[#Solder Pad|solder pad setting]]
7654 3210
---- ----
.... PPPP
      ||||
      ++++- PRG Base A24..A21
Power-on value: $00
==PRG Base Register MSB ($4800), Submapper 5 only==
Mask: $F800
7654 3210
---- ----
..PP PPPP
  || ||||
  ++-++++- PRG Base A24..A19
   
   
  Power-on value: $00
  Power-on value: $00
==CHR Base Register ($5xx2)==
Mask: $5''xx''3, ''x'' determined by [[#DIP Switch|DIP Switch setting]]


==CHR Base Register LSB ($5xx2)==
Mask: $F''xx''7 ('''Submapper 3'''), $5''xx''3 (all others), ''x'' determined by [[#Solder Pad|solder pad setting]]
  7654 3210
  7654 3210
  ---- ----
  ---- ----
  CPCC CCCC
  ccdC CCCC
  |||| ||||
  |||| ||||
  ++++-++++- 8 KiB CHR Base bits 0-7
  ++++-++++- CHR A20..A13
  |
||+------- PRG A25 ('''Submapper 2''' only)
  +-------- 16 KiB PRG Base bit 9
++-------- PRG A24..A23 ('''Submapper 2''' only)
+--------- PRG A21 ('''Submapper 4''')
   
   
  Power-on value: $00
  Power-on value: $00
Writing to the CHR Base Register also resets the CNROM latch.


==Extended Mode Register ($5xx3)==
Depending on the CHR banking mode set via $5xx0, only the higher bits of this register are applied:
Mask: $5''xx''3, ''x'' determined by [[#DIP Switch|DIP Switch setting]]
CHR A..
21111111111
09876543210
-----------
BBBMMMMMMMM  MMC3 CHR Mode ($5xx0.6=0), 256 KiB ($5xx0.4=0)
BBBBMMMMMMM  MMC3 CHR Mode ($5xx0.6=0), 128 KiB ($5xx0.4=1)
BBBBBBLLPPP  CNROM CHR Mode ($5xx0.6=1, $5xx0.5=0), 32 KiB ($5xx0.4=0), '''Submapper 1''' only
BBBBBBBLPPP  CNROM CHR Mode ($5xx0.6=1, $5xx0.5=0), 16 KiB ($5xx0.4=1), '''Submapper 1''' only
BBBBBBBBPPP  NROM CHR Mode ($5xx0.6=1, $5xx0.5=1 or '''Submapper''' other than '''1''')
M: Bit comes from MMC3 ($8000.0-5)
B: Bit comes from CHR Base Register ($5xx2)
L: Bit comes from CNROM Latch ($8000-$FFFF)
P: Bit comes from PPU
 
==CHR Base Register MSB ($5xx6), Submapper 3 only==
Mask: $F''xx''7 ('''Submapper 3'''), ''x'' determined by [[#Solder Pad|solder pad setting]]


  7654 3210
  7654 3210
  ---- ----
  ---- ----
  .C.. .CE.
  .... PPPP
  |   ||  
      ||||
  |    |+- [[#MMC3-compatible registers ($8000/$8001, $A000, $C000/$C001, $E000/$E001)|Extended MMC3 Mode]]
      ++++- CHR Base A24..A21
  |    |    0: disable
  |    |    1: enable
  +----+-- Select NROM/CNROM CHR Mode
            0: NROM
            1: CNROM
   
   
  Power-on value: $00 (Subtypes 0/2), $02 (Subtype 1)
  Power-on value: $00
Since all games that use CNROM mode always set both bits 2 and 6 simultaneously, it's not clear which one of these bits actually triggers the CNROM mode, and what the function of the other bit would be.
 
==Extended Mode Register ($5xx3), Submappers 1-2 only==
Mask: $F''xx''3, ''x'' determined by [[#Solder Pad|solder pad setting]]


==Mirroring Register ($A000, subtype 2 only)==
7654 3210
  Mask: $E001
---- ----
.?.. .?E.
        |
        +- [[#MMC3-compatible registers ($8000/$8001, $A000, $C000/$C001, $E000/$E001)|Extended MMC3 Mode]]
            0: disable
            1: enable
Power-on value: $00
Most multicarts write value $44 rather than $00 to disable Extended MMC3 Mode. Hardware tests do not indicate any difference in behavior between writing $00 and $44.
==Mirroring Register ($A000)==
  Mask: $E003
   
   
  7654 3210
  7654 3210
Line 104: Line 169:
             0: Vertical
             0: Vertical
             1: Horizontal
             1: Horizontal
             2: Single-screen, page 0
             2: Single-screen, page 0 ('''Submapper 2''' only)
             3: Single-screen, page 1
             3: Single-screen, page 1 ('''Submapper 2''' only)
  Power-on value: $00
  Power-on value: $00


The Waixing FS005/Bensheng BS001 supports single-screen mirroring, unlike an original MMC3. Extended MMC3 mode does not have to be enabled.
Single-screen mirroring is only available when the RAM Configuration Register is enabled ($A001.5).


==RAM Configuration Register ($A001)==
==RAM Configuration Register ($A001), Submapper 2 only==
Mask: $E001
Mask: $E003


This register functions like MMC3 register $A001 until bit 5 is set, which turns it into the RAM Configuration Register. It only exists on the Waixing FS005/FS006 boards.
This register functions like MMC3 register $A001 until bit 5 is set, which turns it into the RAM Configuration Register.


  7654 3210
  7654 3210
Line 127: Line 192:
  ||          0: RAM Configuration Register disabled, $A001 functions as on MMC3, 8 KiB of WRAM
  ||          0: RAM Configuration Register disabled, $A001 functions as on MMC3, 8 KiB of WRAM
  ||          1: RAM Configuration Register enabled, 32 KiB of WRAM
  ||          1: RAM Configuration Register enabled, 32 KiB of WRAM
  |+-------- FK23C Registers Enable. Ignored if Bit 5 is clear.
  |+-------- Outer Bank Registers Enable. Ignored if Bit 5 is clear.
  |          0: FK23C Registers disabled, $5000-$5FFF maps to the second 4 KiB of the 8 KiB WRAM bank 2
  |          0: Outer Bank Registers disabled, $5000-$5FFF maps to the second 4 KiB of the 8 KiB WRAM bank 2
  |          1: FK23C Registers enabled in the $5000-$5FFF range
  |          1: Outer Bank Registers enabled in the $5000-$5FFF range
  +--------- PRG RAM enable (0: disable, 1: enable)
  +--------- PRG RAM enable (0: disable, 1: enable)
   
   
  Power-on value: $00
  Power-on value: $00
==CNROM latch ($8000-$9FFF, $C000-$FFFF)==
 
In CNROM Mode, writing to these address ranges changes the inner CHR bank.
==UNROM latch ($8000-$FFFF)==
In UNROM Mode (PRG Mode 5), writing to this address range changes the 16 KiB inner PRG bank at $8000-$BFFF.
 
==CNROM latch ($8000-$FFFF), Submapper 1 only==
In CNROM Mode, writing to this address range changes the inner CHR bank.


==MMC3-compatible registers, Extended MMC3 Mode ($8000/$8001, $C000/$C001, $E000/$E001)==
==MMC3-compatible registers, Extended MMC3 Mode ($8000/$8001, $C000/$C001, $E000/$E001)==
If the "Extended MMC3 Mode" bit in register $5xx3 is clear, then these registers function identically to the [[MMC3]]. If the "Extended MMC3 Mode" bit is set, four more bank registers become available at [[MMC3#Bank_select_.28.248000-.249FFE.2C_even.29|$8000/$8001]], so that the original two 2 KiB CHR banks become four 1 KiB CHR banks, and the two fixed 8 KiB PRG banks become selectable, similar to the [[RAMBO-1]]. Furthermore, all eight bits of the PRG-ROM bank numbers will then be used, allowing up to 2 MiB to be bankedswitched, and all "mask" settings of register $5000 are ignored.
Mask: $E003 (verified on real hardware)
  Register $8000 if $5xx3 bit 1 is set (Mask: $E001):
 
Some multicart games depend on writes to $9FFF not doing anything as a result of the MMC3 address mask being $E003 rather than the standard $E001.
 
If the "Extended MMC3 Mode" bit in register $5xx3 is clear, then these registers function identically to the [[MMC3]]. On '''Submappers 1 and 2''', if the "Extended MMC3 Mode" bit is set, four more bank registers become available at [[MMC3#Bank_select_.28.248000-.249FFE.2C_even.29|$8000/$8001]], so that the original two 2 KiB CHR banks become four 1 KiB CHR banks, and the two fixed 8 KiB PRG banks become selectable, similar to the [[RAMBO-1]].  Register $8000 if $5xx3 bit 1 is set:
  7  bit  0
  7  bit  0
  ---- ----
  ---- ----
Line 162: Line 234:
  * Standard MMC3 Registers $0-$7: $00, $02, $04, $05, $06, $07, $00, $01
  * Standard MMC3 Registers $0-$7: $00, $02, $04, $05, $06, $07, $00, $01
  * Extended MMC3 Registers $8-$B: $FE, $FF, $FF, $FF
  * Extended MMC3 Registers $8-$B: $FE, $FF, $FF, $FF
=DIP Switch=
 
The address mask in the $5000-$5FFF range is determined by the DIP switch setting:
=Solder Pad=
  DIP setting  Address mask
The address mask in the $5000-$5FFF range is determined by the solder pad setting:
  Pad setting  Address mask
  -----------  ------------
  -----------  ------------
  0            $5013
  0            $5013
Line 174: Line 247:
  6            $5403
  6            $5403
  7            $5803
  7            $5803
* A DIP setting of zero (address mask $5013) will produce a usable result for any ROM image.
* A solder pad setting of zero (address mask $5013) will produce a usable result for any ROM image.
* Some multicarts only display their menu at settings other than 0.
* Some multicarts only display their menu at settings other than 0.


=Protection=
=Protection (Submapper 2 only)=
Later Waixing games (and re-releases of earlier games) use the RAM Configuration Register for copy-protection purposes:
Later Waixing games (and re-releases of earlier games) use the RAM Configuration Register for copy-protection purposes:
* Write $A1 to $A001: Address range $5000-$5FFF to second half of 8 KiB WRAM bank 2, mapper registers there are disabled.
* Write $A1 to $A001: Address range $5000-$5FFF to second half of 8 KiB WRAM bank 2, mapper registers there are disabled.
Line 187: Line 260:
* Execute code at CPU $0100.
* Execute code at CPU $0100.
Hacked ROMs can be detected by them writing to $5000/$5010/$5013 but then no longer jumping to $0100.
Hacked ROMs can be detected by them writing to $5000/$5010/$5013 but then no longer jumping to $0100.
 
=See also=
=Notes=
* [[NES 2.0 Mapper 523]] is a variant of this mapper with hard-wired mirroring that connects CHR-ROM differently to produce 4/2 KiB instead of 2/1 KiB banks.
* Multicarts without CHR-ROM have large amounts of CHR-RAM into which an individual game's CHR data is copied when it is selected:
** 128 KiB: 10-in-1 Omake Game, 150-in-1 Real Game, 245-in-1 Real Game
** 256 KiB: 120-in-1 (Waixing)
* Waixing re-released some of their earlier games, that were originally published using other mappers, in the mid-2000s using their FS005/BS001 board, often without updating the serial number.
* There are about 60 multicarts and about 52 single Waixing games, including rereleases, using Mapper 176.
* The FS005/BS001 board does not work in standard Nintendo (AV) Famicoms, only on Famiclones, due to not driving the CIRAM /CE signal correctly.
=Errata=
* Games using advanced functionalites such as Extended MMC3 Mode or 32 KiB WRAM have duplicates in some emulators' implementations of [[INES Mapper 030]], [[INES Mapper 074]] and [[INES Mapper 199]]. As these mapper numbers are also used for other boards, these games should be reassigned to Mapper 176 instead of adding Mapper 176 functionality to Mappers 30, 74 and 199.
* GoodNES 3.23b's "Mortal Kombat Trilogy - 8 People (M1274) (Ch) [!]" is actually the "KY-9005 9-in-1" multicart and runs on [[NES 2.0 Mapper 260]].
* ''帝国风暴 (Dìguó Fēngbào) - Napoleon's War'' with copyright number 980340 requires PAL or Dendy timing to not freeze before the main game screen is shown. Copyright number 980100029 does not suffer from this problem.
* ''龙域天下'' (Lóng yù Tiānxià), Waixing's Chinese localization of ''Radia Senki: Reimeihen'', requires PAL or Dendy timing to not glitch and eventually freeze during the introduction.
* ''Five Kids'' on the ''120-in-1'' multicart writes to [[VT03|OneBus]] bank registers in its IRQ handler and glitches on normal NES/Famicom hardware.
* The menus of several multicarts using this mapper time their music by polling $2002 bit 7 but do not take the [[NMI#Race_condition|race condition]] into account. As a result, its music is audibly slowed down irregularly when played on an original NES/Famicom console.
* The menus of several multicarts using this mapper have a game selection cursor that changes its position erratically with [[Standard controller|original Nintendo controllers]] or any controller that returns 1 rather than 0 after all buttons have been read via $4016.

Latest revision as of 18:48, 17 December 2021

iNES Mapper 176 denotes the 8025 enhanced MMC3 chipset. It used by many multicarts, Chinese single-game and educational computer cartridges, and Techno Source's Intellivision X2 Plug-and-Play console. Incompatible variations exist that are denoted via NES 2.0 Submapper.

Submappers
# PCB codes UNIF MAPR MMC3 Outer bank registers Example
Ext. mode PRG bits $46/47 1SM Extra WRAM Address mask PRG A21+ CHR A21+ CNROM latch
0 LP-8002KB, SFC-12B BMC-Super24in1SC03 - 6 normal - - $Fxx3 - - - YH-xxx multicarts, Rockman 6-in-1
1 FK-xxx/BS-xxx BMC-FK23C/BMC-FK23CA $5FF3.1 8 normal - - $Fxx3 - - yes FK-xxxx multicarts
2 FS005/FS006 WAIXING-FS005 $5FF3.1 6 swapped yes $A001.0-1 $Fxx3 $5xx0.3/7, $5xx2.6-7/5 - - Waixing 2005+ re-releases, 245-in-1 Real Game
3 JX9003B - - 8 normal - - $Fxx7 $5xx5 $5xx6 - Super Mario 160-in-1 Funny Time
4 ? - - 6 normal - - $Fxx3 $5xx2.7 - - GameStar Smart Genius Deluxe
5 HST-162 - - 6 normal - - $Fxx3 $4800 - - Game 500-in-1
  • The SFC-12B PCB (submapper 0) mounts both CHR-ROM and CHR-RAM that are selected via $5xx0.5.
  • Eight MMC3 PRG bits mean that bit 6 and 7 of $8000.6/7 are applied, and the fixed banks are $FE/$FF rather than $3E/$3F. This implies that the multicart's reset vector lies at address PRG-ROM address $1FFFFC rather than $7FFFC if the PRG-ROM is that large.

Registers

FS005 (Submapper 2) can disable the registers in the $5000-$5FFF range using the RAM Configuration Register ($A001). The same register also enables a mixed CHR-ROM/CHR-RAM mode that is similar to INES Mapper 195.

Mode Register ($5xx0)

Mask: $Fxx7 (Submapper 3), $5xx3 (all others), x determined by solder pad setting 

7654 3210
---- ----
PCTm PMMM
|||| ||||
|||| |+++- Select PRG Banking Mode (ignored in Extended MMC3 Mode)
|||| |      0: MMC3 PRG Mode, 2 MiB/512 KiB Outer PRG Bank Size
|||| |      1: MMC3 PRG Mode, 256 KiB Outer PRG Bank Size
|||| |      2: MMC3 PRG Mode, 128 KiB Outer PRG Bank Size
|||| |      3: NROM-128 PRG Mode, 16 KiB PRG at $8000-$BFFF mirrored at $C000-$FFFF
|||| |      4: NROM-256 PRG Mode, 32 KiB PRG at $8000-$FFFF
|||| |      5: UNROM PRG Mode, 16 KiB PRG at $8000-$BFFF, inner bank #7 at $C000-$FFFF
|||| |      6-7: Never used
|||| +---- PRG A21 (Submapper 2 only)
|||+------ Select Outer CHR Bank Size
|||         0: In MMC3 CHR Mode: 256 KiB
|||            In CNROM CHR Mode: 32 KiB (Submapper 1 only)
|||         1: In MMC3 CHR Mode: 128 KiB
|||            In CNROM CHR Mode: 16 KiB (Submapper 1 only)
||+------- Submappers 0/1 with both CHR-ROM and CHR-RAM (e.g. SFC-12B PCB):
||          0: Select CHR-ROM
||          1: Select CHR-RAM
||         Submapper 1 with $5xx0.6=1:
||          0: Enable CNROM latch (CNROM mode)
||          1: Disable CNROM latch (NROM mode)
|+-------- CHR A10-12 Mode
|           0: from MMC3
|           1: from PPU
+--------- PRG A22 (Submapper 2 only)

Power-on value: $00

PRG Base Register LSB ($5xx1)

Mask: $Fxx7 (Submapper 3), $Fxx3 (all others), x determined by solder pad setting 

7654 3210
---- ----
.PPP PPPP
 ||| ||||
 +++-++++- PRG A20..A14

Power-on value: $00

Depending on the PRG banking mode set via $5xx0, only the higher bits of this register are applied: 

PRG A..
21111111
09876543
--------
MMMMMMMM  Submappers 1/3 in PRG Mode 0 (MMC3 2 MiB) or Extended MMC3 Mode
BBMMMMMM  Submappers 0/2/4 in PRG Mode 0 (MMC3 512 KiB)
BBBMMMMM  PRG Mode 1 (MMC3 256 KiB)
BBBBMMMM  PRG Mode 2 (MMC3 128 KiB)
BBBBBBBC  PRG Mode 3 (NROM-128)
BBBBBBCC  PRG Mode 4 (NROM-256)
BBBBLLLC  PRG Mode 5 (UNROM)

M: Bit comes from MMC3 ($8000.6/7 or fixed bank)
B: Bit comes from PRG Base Register ($5xx1)
L: Bit comes from UNROM Latch ($8000-$FFFF or fixed bank)
C: Bit comes from CPU

Submapper 5 only selects PRG A14-A18 (i.e. 512 KiB) via this register, selecting upper PRG bits via register $4800.

PRG Base Register MSB ($5xx5), Submapper 3 only

Mask: $Fxx7 (Submapper 3), x determined by solder pad setting 

7654 3210
---- ----
.... PPPP
     ||||
     ++++- PRG Base A24..A21

Power-on value: $00

PRG Base Register MSB ($4800), Submapper 5 only

Mask: $F800 

7654 3210
---- ----
..PP PPPP
  || ||||
  ++-++++- PRG Base A24..A19

Power-on value: $00

CHR Base Register LSB ($5xx2)

Mask: $Fxx7 (Submapper 3), $5xx3 (all others), x determined by solder pad setting 

7654 3210
---- ----
ccdC CCCC
|||| ||||
++++-++++- CHR A20..A13
||+------- PRG A25 (Submapper 2 only)
++-------- PRG A24..A23 (Submapper 2 only)
+--------- PRG A21 (Submapper 4)

Power-on value: $00

Depending on the CHR banking mode set via $5xx0, only the higher bits of this register are applied: 

CHR A..
21111111111
09876543210
-----------
BBBMMMMMMMM  MMC3 CHR Mode ($5xx0.6=0), 256 KiB ($5xx0.4=0)
BBBBMMMMMMM  MMC3 CHR Mode ($5xx0.6=0), 128 KiB ($5xx0.4=1)
BBBBBBLLPPP  CNROM CHR Mode ($5xx0.6=1, $5xx0.5=0), 32 KiB ($5xx0.4=0), Submapper 1 only
BBBBBBBLPPP  CNROM CHR Mode ($5xx0.6=1, $5xx0.5=0), 16 KiB ($5xx0.4=1), Submapper 1 only
BBBBBBBBPPP  NROM CHR Mode ($5xx0.6=1, $5xx0.5=1 or Submapper other than 1)

M: Bit comes from MMC3 ($8000.0-5)
B: Bit comes from CHR Base Register ($5xx2)
L: Bit comes from CNROM Latch ($8000-$FFFF)
P: Bit comes from PPU

CHR Base Register MSB ($5xx6), Submapper 3 only

Mask: $Fxx7 (Submapper 3), x determined by solder pad setting 

7654 3210
---- ----
.... PPPP
     ||||
     ++++- CHR Base A24..A21

Power-on value: $00

Extended Mode Register ($5xx3), Submappers 1-2 only

Mask: $Fxx3, x determined by solder pad setting 

7654 3210
---- ----
.?.. .?E.
       | 
       +- Extended MMC3 Mode
           0: disable
           1: enable

Power-on value: $00

Most multicarts write value $44 rather than $00 to disable Extended MMC3 Mode. Hardware tests do not indicate any difference in behavior between writing $00 and $44.

Mirroring Register ($A000)

Mask: $E003

7654 3210
---- ----
.... ..MM
       ++- Select nametable mirroring 
           0: Vertical
           1: Horizontal
           2: Single-screen, page 0 (Submapper 2 only)
           3: Single-screen, page 1 (Submapper 2 only)
Power-on value: $00

Single-screen mirroring is only available when the RAM Configuration Register is enabled ($A001.5).

RAM Configuration Register ($A001), Submapper 2 only

Mask: $E003

This register functions like MMC3 register $A001 until bit 5 is set, which turns it into the RAM Configuration Register. 

7654 3210
---- ----
RFE. SCWW
|||  ||||
|||  ||++- Select 8 KiB PRG-RAM bank at $6000-$7FFF. Ignored if Bit 5 is clear.
|||  |+--- Select the memory type in the first 8 KiB of CHR space. Ignored if Bit 5 is clear.
|||  |      0: First 8 KiB are CHR-ROM
|||  |      1: First 8 KiB are CHR-RAM
|||  +---- Unknown
||+------- RAM Configuration Register Enable
||          0: RAM Configuration Register disabled, $A001 functions as on MMC3, 8 KiB of WRAM
||          1: RAM Configuration Register enabled, 32 KiB of WRAM
|+-------- Outer Bank Registers Enable. Ignored if Bit 5 is clear.
|           0: Outer Bank Registers disabled, $5000-$5FFF maps to the second 4 KiB of the 8 KiB WRAM bank 2
|           1: Outer Bank Registers enabled in the $5000-$5FFF range
+--------- PRG RAM enable (0: disable, 1: enable)

Power-on value: $00

UNROM latch ($8000-$FFFF)

In UNROM Mode (PRG Mode 5), writing to this address range changes the 16 KiB inner PRG bank at $8000-$BFFF.

CNROM latch ($8000-$FFFF), Submapper 1 only

In CNROM Mode, writing to this address range changes the inner CHR bank.

MMC3-compatible registers, Extended MMC3 Mode ($8000/$8001, $C000/$C001, $E000/$E001)

Mask: $E003 (verified on real hardware)

Some multicart games depend on writes to $9FFF not doing anything as a result of the MMC3 address mask being $E003 rather than the standard $E001.

If the "Extended MMC3 Mode" bit in register $5xx3 is clear, then these registers function identically to the MMC3. On Submappers 1 and 2, if the "Extended MMC3 Mode" bit is set, four more bank registers become available at $8000/$8001, so that the original two 2 KiB CHR banks become four 1 KiB CHR banks, and the two fixed 8 KiB PRG banks become selectable, similar to the RAMBO-1. Register $8000 if $5xx3 bit 1 is set: 

7  bit  0
---- ----
CP.. RRRR
||   ||||
||   ++++- Specify which bank register to update on next write to Bank Data register
||         $0: Select 1 KB CHR bank at PPU $0000-$03FF (or $1000-$13FF)
||         $1: Select 1 KB CHR bank at PPU $0800-$0BFF (or $1800-$1BFF)
||         $2: Select 1 KB CHR bank at PPU $1000-$13FF (or $0000-$03FF)
||         $3: Select 1 KB CHR bank at PPU $1400-$17FF (or $0400-$07FF)
||         $4: Select 1 KB CHR bank at PPU $1800-$1BFF (or $0800-$0BFF)
||         $5: Select 1 KB CHR bank at PPU $1C00-$1FFF (or $0C00-$0FFF)
||         $6: Select 8 KB PRG ROM bank at $8000-$9FFF (or $C000-$DFFF)
||         $7: Select 8 KB PRG ROM bank at $A000-$BFFF
||         $8: Select 8 KB PRG ROM bank at $C000-$DFFF (or $8000-$9FFF)
||         $9: Select 8 KB PRG ROM bank at $E000-$FFFF
||         $A: Select 1 KB CHR bank at PPU $0400-$07FF (or $1400-$17FF)
||         $B: Select 1 KB CHR bank at PPU $0C00-$0FFF (or $1C00-$1FFF)
|+-------- Invert PRG A14
+--------- Invert CHR A12

Power-on values:
* Standard MMC3 Registers $0-$7: $00, $02, $04, $05, $06, $07, $00, $01
* Extended MMC3 Registers $8-$B: $FE, $FF, $FF, $FF

Solder Pad

The address mask in the $5000-$5FFF range is determined by the solder pad setting: 

Pad setting  Address mask
-----------  ------------
0            $5013
1            $5023
2            $5043
3            $5083
4            $5103
5            $5203
6            $5403
7            $5803
  • A solder pad setting of zero (address mask $5013) will produce a usable result for any ROM image.
  • Some multicarts only display their menu at settings other than 0.

Protection (Submapper 2 only)

Later Waixing games (and re-releases of earlier games) use the RAM Configuration Register for copy-protection purposes:

  • Write $A1 to $A001: Address range $5000-$5FFF to second half of 8 KiB WRAM bank 2, mapper registers there are disabled.
  • Write three values to $5000, $5010 and $5013.
  • Do further initialization.
  • Write $E2 to $A001. Mapper registers in address range $5000-$5FFF; WRAM at CPU $6000-$7FFF points to 8 KiB WRAM bank 2.
  • Copy 20 bytes from $7000 to $6000.
  • Copy and XOR bytes from $6000, $6010 and $6013 to $0100-$0102.
  • Execute code at CPU $0100.

Hacked ROMs can be detected by them writing to $5000/$5010/$5013 but then no longer jumping to $0100.

See also

  • NES 2.0 Mapper 523 is a variant of this mapper with hard-wired mirroring that connects CHR-ROM differently to produce 4/2 KiB instead of 2/1 KiB banks.
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