APU Noise: Difference between revisions

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m (Created page with 'The NES APU triangle channel generates a pseudo-triangle wave. It has no volume control; the waveform is either cycling or suspended. It includes a ''linear counter'', an...')
 
(Clarify that noise period table is specified in CPU clocks)
 
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The [[APU|NES APU]] triangle channel generates a pseudo-triangle wave. It has no volume control; the waveform is either cycling or suspended. It includes a ''linear counter'', an extra duration timer of higher accuracy than the [[APU Length Counter|length counter]].
[[Category:APU]]
The [[APU|NES APU]] noise channel generates pseudo-random 1-bit noise at 16 different frequencies.
 
The noise channel contains the following: [[APU Envelope|envelope generator]], [[APU Misc|timer]], [[wikipedia:Linear_feedback_shift_register|Linear Feedback Shift Register]], [[APU Length Counter|length counter]].


The triangle channel contains the following: [[APU Misc|timer]], linear counter, [[APU Length Counter|length counter]], halt flag, [[APU Misc|sequencer]]. The linear counter contains an internal halt flag and counter.
<pre>
<pre>
      Linear Counter   Length Counter
  Timer --> Shift Register   Length Counter
            |                |
                  |                |
            v                v
                  v                v
Timer ---> Gate ----------> Gate ---> Sequencer ---> (to mixer)
Envelope -------> Gate ----------> Gate --> (to mixer)
</pre>
</pre>


{| border=1
{| border=1
| '''$4008''' || <tt>CRRR.RRRR</tt> || '''Linear counter''' setup (write)
| '''$400C''' || <tt>--lc.vvvv</tt> || '''[[APU Length Counter|Length counter halt]]''', constant volume/envelope flag, and volume/'''[[APU Envelope|envelope]]''' divider period (write)
|-
|-
| bit 7 || <tt>C---.----</tt> || Control flag (this bit is also the [[APU Length Counter|length counter halt flag]])
|colspan=3| &nbsp;
|-
|-
| bits 6-0 || <tt>-RRR RRRR</tt> || Counter reload value
| '''$400E''' || <tt>M---.PPPP</tt> || '''Mode and period''' (write)
|-
|-
|colspan=3| &nbsp;
| bit 7 || <tt>M--- ----</tt> || Mode flag
|-
|-
| '''$400A''' || <tt>LLLL.LLLL</tt> || '''[[APU Misc|Timer low]]''' (write)
| bits 3-0 || <tt>---- PPPP</tt> || The timer period is set to entry P of the following:<br>
|-
<!-- If you modify this table, keep the values comma-separated so they can be used without changes in a program -->
| bits 7-0 || <tt>LLLL LLLL</tt> || Timer low 8 bits
<pre>
Rate  $0 $1  $2  $3  $4  $5  $6  $7   $8  $9  $A  $B  $C    $D    $E    $F
      --------------------------------------------------------------------------
NTSC  4, 8, 16, 32, 64, 96, 128, 160, 202, 254, 380, 508, 762, 1016, 2034, 4068
PAL    4, 8, 14, 30, 60, 88, 118, 148, 188, 236, 354, 472, 708,  944, 1890, 3778
</pre>
The period determines how many CPU cycles happen between shift register clocks.<br>
These periods are all even numbers because there are 2 CPU cycles in an APU cycle.
|-
|-
|colspan=3| &nbsp;
|colspan=3| &nbsp;
|-
|-
| '''$400B''' || <tt>llll.lHHH</tt> || '''[[APU Length Counter|Length counter load]]''' and '''[[APU Misc|timer high]]''' (write)
| '''$400F''' || <tt>llll.l---</tt> || '''[[APU Length Counter|Length counter load]]''' and '''[[APU Envelope|envelope restart]]''' (write)
|-
| bits 2-0 || <tt>---- -HHH</tt> || Timer high 3 bits
|-
|colspan=2| Side effects || Sets the halt flag
|}
|}


The [[APU Misc|timer's period]] is the 11-bit value (<tt>%HHH.LLLLLLLL</tt>) formed by timer high and timer low, ''plus one''.
The shift register is 15 bits wide, with bits numbered<br>
14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0
 
When the timer clocks the shift register, the following actions occur in order:
 
# Feedback is calculated as the exclusive-OR of bit 0 and one other bit: bit 6 if Mode flag is set, otherwise bit 1.
# The shift register is shifted right by one bit.
# Bit 14, the leftmost bit, is set to the feedback calculated earlier.


When the [[APU Frame Counter|frame counter]] generates a linear counter clock, the following actions occur in order:
This results in a pseudo-random bit sequence, 32767 steps long when Mode flag is clear, and randomly 93 or 31 steps long otherwise. (The particular 31- or 93-step sequence depends on where in the 32767-step sequence the shift register was when Mode flag was set).
# If the halt flag is set, the linear counter is reloaded with the counter reload value, otherwise if the linear counter is non-zero, it is decremented.
# If the control flag is clear, the halt flag is cleared.


The sequencer is clocked by the timer except when
The [[APU Mixer|mixer]] receives the current [[APU Envelope|envelope volume]] except when
* The linear counter is zero, or
* Bit 0 of the shift register is set, or
* The [[APU Length Counter|length counter]] is zero
* The [[APU Length Counter|length counter]] is zero


The sequencer sends the following looping 32-step sequence of values to the [[APU Mixer|mixer]]:
Within the mixer, the DMC level has a noticeable effect on the noise's level.
<pre>
 
15, 14, 13, 12, 11, 10,  9,  8,  7,  6,  5,  4,  3,  2,  1, 0
On power-up, the shift register is loaded with the value 1.
0,  1, 2, 3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15
 
</pre>
In the earliest revisions of the 2A03 CPU, the Mode flag was nonexistent and the shift register always used bits 0 and 1 for feedback. These CPUs were used in the first batch of Famicom consoles (which were recalled), in Vs. System boards, and in the arcade games that used the 2A03 as a sound coprocessor.[http://forums.nesdev.org/viewtopic.php?p=58046#p58046]


At the lowest two [[APU Misc|timer]] periods ($400B = 0 and $400A = 0 or 1), the resulting frequency is so high that the [[APU Mixer|mixer]] effectively receives a value half way between 7 and 8.
The 93-step sequence is about a quarter tone (50 cents) sharp relative to A440 tuning. The approximate frequencies and pitches (in [[wikipedia:Helmholtz pitch notation#Variations|LilyPond's variant of Helmholtz notation]]) are as follows:
<!-- Generated with https://github.com/pinobatch/pently/blob/master/tools/noise_freqs.py -->
{| class="wikitable"
|+ Pitches of 93-step noise on NTSC
! Period setting || Sample rate || Fundamental || MIDI note || Pitch
|-
| $80 || 447443.2 Hz || 4811.2 Hz || 110.41 || <nowiki>d''''' + 41¢</nowiki>
|-
| $81 || 223721.6 Hz || 2405.6 Hz || 98.41 || <nowiki>d'''' + 41¢</nowiki>
|-
| $82 || 111860.8 Hz || 1202.8 Hz || 86.41 || <nowiki>d''' + 41¢</nowiki>
|-
| $83 || 55930.4 Hz || 601.4 Hz || 74.41 || <nowiki>d'' + 41¢</nowiki>
|-
| $84 || 27965.2 Hz || 300.7 Hz || 62.41 || d' + 41¢
|-
| $85 || 18643.5 Hz || 200.5 Hz || 55.39 || g + 39¢
|-
| $86 || 13982.6 Hz || 150.4 Hz || 50.41 || d + 41¢
|-
| $87 || 11186.1 Hz || 120.3 Hz || 46.55 || a#, + 55¢
|-
| $88 || 8860.3 Hz || 95.3 Hz || 42.51 || f#, + 51¢
|-
| $89 || 7046.3 Hz || 75.8 Hz || 38.55 || d, + 55¢
|-
| $8A || 4709.9 Hz || 50.6 Hz || 31.57 || g,, + 57¢
|-
| $8B || 3523.2 Hz || 37.9 Hz || 26.55 || d,, + 55¢
|-
| $8C || 2348.8 Hz || 25.3 Hz || 19.53 || g,,, + 53¢
|-
| $8D || 1761.6 Hz || 18.9 Hz || 14.55 || d,,, + 55¢
|-
| $8E || 879.9 Hz || 9.5 Hz || 2.53 || d,,,, + 53¢
|-
| $8F || 440.0 Hz || 4.7 Hz || -9.47 || d,,,,, + 53¢
|}

Latest revision as of 20:32, 27 September 2023

The NES APU noise channel generates pseudo-random 1-bit noise at 16 different frequencies.

The noise channel contains the following: envelope generator, timer, Linear Feedback Shift Register, length counter. 

   Timer --> Shift Register   Length Counter
                   |                |
                   v                v
Envelope -------> Gate ----------> Gate --> (to mixer)
$400C --lc.vvvv Length counter halt, constant volume/envelope flag, and volume/envelope divider period (write)
 
$400E M---.PPPP Mode and period (write)
bit 7 M--- ---- Mode flag
bits 3-0 ---- PPPP The timer period is set to entry P of the following:
Rate  $0 $1  $2  $3  $4  $5   $6   $7   $8   $9   $A   $B   $C    $D    $E    $F
      --------------------------------------------------------------------------
NTSC   4, 8, 16, 32, 64, 96, 128, 160, 202, 254, 380, 508, 762, 1016, 2034, 4068
PAL    4, 8, 14, 30, 60, 88, 118, 148, 188, 236, 354, 472, 708,  944, 1890, 3778

The period determines how many CPU cycles happen between shift register clocks.
These periods are all even numbers because there are 2 CPU cycles in an APU cycle.

 
$400F llll.l--- Length counter load and envelope restart (write)

The shift register is 15 bits wide, with bits numbered
14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0

When the timer clocks the shift register, the following actions occur in order:

  1. Feedback is calculated as the exclusive-OR of bit 0 and one other bit: bit 6 if Mode flag is set, otherwise bit 1.
  2. The shift register is shifted right by one bit.
  3. Bit 14, the leftmost bit, is set to the feedback calculated earlier.

This results in a pseudo-random bit sequence, 32767 steps long when Mode flag is clear, and randomly 93 or 31 steps long otherwise. (The particular 31- or 93-step sequence depends on where in the 32767-step sequence the shift register was when Mode flag was set).

The mixer receives the current envelope volume except when

Within the mixer, the DMC level has a noticeable effect on the noise's level.

On power-up, the shift register is loaded with the value 1.

In the earliest revisions of the 2A03 CPU, the Mode flag was nonexistent and the shift register always used bits 0 and 1 for feedback. These CPUs were used in the first batch of Famicom consoles (which were recalled), in Vs. System boards, and in the arcade games that used the 2A03 as a sound coprocessor.[1]

The 93-step sequence is about a quarter tone (50 cents) sharp relative to A440 tuning. The approximate frequencies and pitches (in LilyPond's variant of Helmholtz notation) are as follows:

Pitches of 93-step noise on NTSC
Period setting Sample rate Fundamental MIDI note Pitch
$80 447443.2 Hz 4811.2 Hz 110.41 d''''' + 41¢
$81 223721.6 Hz 2405.6 Hz 98.41 d'''' + 41¢
$82 111860.8 Hz 1202.8 Hz 86.41 d''' + 41¢
$83 55930.4 Hz 601.4 Hz 74.41 d'' + 41¢
$84 27965.2 Hz 300.7 Hz 62.41 d' + 41¢
$85 18643.5 Hz 200.5 Hz 55.39 g + 39¢
$86 13982.6 Hz 150.4 Hz 50.41 d + 41¢
$87 11186.1 Hz 120.3 Hz 46.55 a#, + 55¢
$88 8860.3 Hz 95.3 Hz 42.51 f#, + 51¢
$89 7046.3 Hz 75.8 Hz 38.55 d, + 55¢
$8A 4709.9 Hz 50.6 Hz 31.57 g,, + 57¢
$8B 3523.2 Hz 37.9 Hz 26.55 d,, + 55¢
$8C 2348.8 Hz 25.3 Hz 19.53 g,,, + 53¢
$8D 1761.6 Hz 18.9 Hz 14.55 d,,, + 55¢
$8E 879.9 Hz 9.5 Hz 2.53 d,,,, + 53¢
$8F 440.0 Hz 4.7 Hz -9.47 d,,,,, + 53¢
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