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| [[Category:INES Mappers|006]][[Category:Mappers with cycle IRQs]] | | {{DEFAULTSORT:006}}[[Category:INES Mappers]][[Category:Mappers with cycle IRQs]] |
| iNES Mapper 006 is used for ROM images that have been extracted from disk images for the ''Bung (Super) Game Doctor'' or ''Front Fareast Magicard'' [[RAM cartridge|RAM cartridges]] and that use [[#Mode 1: Custom|Game Doctor Mode 1]] or [[#8 KiB PRG Banking Mode|8 KiB PRG Banking Mode]] (exclusively or non-exclusively). iNES Mapper 008 specifies [[#Mode 4: GNROM|Game Doctor Mode 4]], which makes it a duplicate of [[INES Mapper 066]]. Extracted games that exclusively use the other banking modes can be run using their normal [[iNES]] mapper equivalents, provided that WRAM at $6000-$7FFF is emulated, [[PRG RAM circuit|as implied by the iNES format]]. | | '''iNES Mapper 006''' denotes ROM images that have been extracted from disk images for the ''Front Fareast Magic Card 1M'' or ''2M'' [[RAM cartridge|RAM cartridges]]. They represent games whose [[Game_Doctor/Magic_Card_FDS_Format#Front_Fareast_Magic_Card_1M.2F2M.2F4M_disks|Doctor Header file]] denotes a Magic Card 1M/2M disk (byte $0 bit 7 set, bits 4 and 5 clear, byte $7=$00). Refer to the [[Super Magic Card]] article for details on bankswitching. The Super Magic Card's registers are initialized to: |
| | ; Play mode, WRAM bank 0, 1 KiB CHR mode disabled |
| | [[Super_Magic_Card#Super_Magic_Card_mode_.28.244500.2C_write-only.29|$4500]] = $42 |
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| | ; PRG memory write-protected, two-screen mirroring |
| | [[Super_Magic_Card#1M_banking_mode_.28.2442FC-.2442FF.2C_write-only.29|$42FF]] = (submapper <<5) | (verticalMirroring? 0x00: 0x10) |
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| | ; 2M/4M banking mode disabled |
| | [[Super_Magic_Card#2M.2F4M_PRG_banking_mode_.28.2443FC-.2443FF.2C_write-only.29|$43FF]] = $00 |
| | The [[NES 2.0]] Submapper field denotes the initial [[Super_Magic_Card#Latch-based_modes|latch-based banking mode]] (0-7). [[INES|NES 1.0]] files correspond to submapper 1. '''iNES [[INES Mapper 008|Mapper 8]]''' is a synonym of Mapper 6 submapper 4. |
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| =Banks=
| | The [[iNES]] header may specify a [[INES#Trainer|512-byte trainer]] (corresponding to [[Game_Doctor/Magic_Card_FDS_Format#Front_Fareast_Magic_Card_1M.2F2M.2F4M_disks|Doctor Header file]]'s byte $0 bit 6 being set), which must be loaded to $7000-$71FF, be writable, and (on a hard reset) initialized by JSRing to $7003 before JMPing to the game's reset vector. |
| * CPU $6000-$7FFF: 8 KiB of PRG-RAM. If the [[iNES]] header specifies a 512-byte "trainer", it must be loaded to $7000-$71FF, be writable, and (on a hard reset) initialized by JSRing to $7003 before JMPing to the game's reset vector.
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| * CPU $8000-$FFFF: 32 KiB of PRG-"ROM", banked in various amounts from 256 KiB total depending on the banking mode.
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| * PPU $0000-$1FFF: 8 KiB of CHR-RAM, banked in 8 KiB amounts from 32 KiB total.
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| =Game Doctor Banking Modes=
| | Battery-saving of WRAM content is not supported by any Magic Card model. Hard-resetting a game while restoring previously-saved WRAM content in emulators interferes with the correct operation of the trainer's program. |
| Write-only register at $42FC-$42FF:
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| A~FEDC BA98 7654 3210 D~7654 3210
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| ------------------- ---------
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| 0100 0010 1111 11bM BBBM ....
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| |+----|||+------ Set nametable mirroring type
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| | ||| 0: One-screen, page 0
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| | ||| 1: One-screen, page 1
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| | ||| 2: Vertical
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| | ||| 3: Horizontal
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| +-----|||------- 0: PRG-ROM is writeable, latch is disabled
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| ||| 1: PRG-ROM is write-protected, latch is enabled
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| +++------- Select Game Doctor Banking mode
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| * Because the RAM cartridge has no other means of masking PRG-/CHR-ROM addresses, UNROM vs. UOROM and CNROM-128 vs. CNROM-256 are explicitly differentiated.
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| * When changing from a mode that allows changing CHR-RAM banks to one that does not, the previously-chosen CHR-RAM bank remains active.
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| * The latch at $8000-$FFFF is only active when PRG-"ROM" is [[#Game Doctor Mode ($42FC-$42FF)|write-protected]]. A few games temporarily write-enable PRG-"ROM" to change the reset vector after initialization.
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| ==Mode 0: [[INES Mapper 002|UNROM]]==
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| * 16 KiB PRG-ROM bank at CPU $8000-$BFFF, switched by D0..D2 of data latch at CPU $8000-$FFFF
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| * 16 KiB PRG-ROM bank at CPU $C000-$FFFF, fixed to bank #7
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| * 8 KiB of write-enabled CHR-RAM
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| ==Mode 1: Custom==
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| A hybrid of [[UNROM]] (fixed bank 7), [[UOROM]] (256 KiB total PRG-ROM size), and [[iNES Mapper 094|UN1ROM]] (left shift by 2) with 32 KiB of CHR-RAM.
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| * 16 KiB PRG-ROM bank at CPU $8000-$BFFF, switched by D2..D6 of data latch at CPU $8000-$FFFF
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| * 16 KiB PRG-ROM bank at CPU $C000-$FFFF, fixed to bank #7
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| * 8 KiB write-enabled CHR-RAM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFF
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| ==Mode 2: [[INES Mapper 002|UOROM]]== | | =See also= |
| * 16 KiB PRG-ROM bank at CPU $8000-$BFFF, switched by D0..D3 of data latch at CPU $8000-$FFFF
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| * 16 KiB PRG-ROM bank at CPU $C000-$FFFF, fixed to bank #15
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| * 8 KiB of write-enabled CHR-RAM
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| ==Mode 3: [[INES Mapper 097|Reverse UOROM]]==
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| * 16 KiB PRG-ROM bank at CPU $8000-$BFFF, fixed to bank #15
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| * 16 KiB PRG-ROM bank at CPU $C000-$FFFF, switched by D0..D3 of data latch at CPU $8000-$FFFF
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| * 8 KiB of write-enabled CHR-RAM
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| ==Mode 4: [[INES Mapper 066|GNROM]]==
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| * 32 KiB PRG-ROM bank at CPU $8000-$FFFF, switched by D4..D5 of data latch at CPU $8000-$FFFF
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| * 8 KiB write-protected CHR-RAM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFF
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| ==Mode 5: [[INES Mapper 003|CNROM-256]]==
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| * 32 KiB PRG-ROM bank at CPU $8000-$FFFF, fixed to bank #7
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| * 8 KiB write-protected CHR-RAM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFF
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| ==Mode 6: [[INES Mapper 003|CNROM-128]]==
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| * 32 KiB PRG-ROM bank at CPU $8000-$FFFF, fixed to bank #3
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| * 8 KiB of write-protected CHR-RAM bank at PPU $0000-$1FFF, switched by D0 of data latch at CPU $8000-$FFFF
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| ==Mode 7: [[INES Mapper 000|NROM-256]]==
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| * 32 KiB PRG-ROM bank at CPU $8000-$FFFF, fixed to bank #3
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| * 8 KiB write-protected CHR-RAM bank at PPU $0000-$1FFF
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| =8 KiB PRG Banking Mode=
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| Write-only register at $43FE-$43FF:
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| A~FEDC BA98 7654 3210
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| -------------------
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| 0100 0011 1111 111M
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| +- Enable/Disable 8 KiB PRG Banking Mode
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| 0: Enable
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| 1: Disable
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| *Banks:
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| ** 8 KiB PRG-ROM bank at CPU $8000-$9FFF, switched by D2..D7 of data latch at CPU $8000-$9FFF
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| ** 8 KiB PRG-ROM bank at CPU $A000-$BFFF, switched by D2..D7 of data latch at CPU $A000-$BFFF
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| ** 8 KiB PRG-ROM bank at CPU $C000-$DFFF, switched by D2..D7 of data latch at CPU $C000-$DFFF
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| ** 8 KiB PRG-ROM bank at CPU $E000-$FFFF, switched by D2..D7 of data latch at CPU $E000-$FFFF
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| ** 8 KiB CHR-RAM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFF
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| * If enabled, it has precedence over the Game Doctor banking modes in everything but CHR-RAM write-protection.
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| * The four data latches accept values written even when 8 KiB Banking Mode is not active, and will take effect once $43FE is written to afterwards.
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| =Non-banking registers=
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| ==FDS Write Data ($4024)==
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| [[Family_Computer_Disk_System#Write_data_register_.28.244024.29|This register]] is not part of the RAM cartridge, but part of the FDS RAM adapter that originally attached to it. A few games abuse the FDS Disk Data IRQ for frame timing and write any value to this register to acknowledge a pending IRQ.
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| That technique is necessary because the RAM cartridge, once activated, no longer relays the cartridge connector's M2 signal to the FDS RAM adapter, making its $4020-$4022 IRQ counter unusable. The Disk Data IRQ still works because it is based on the RAM adapter's own clock source.
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| ==FDS Control ($4025)==
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| [[Family_Computer_Disk_System#FDS_Control_.28.244025.29|This register]] is not part of the RAM cartridge, but part of the FDS RAM adapter that originally attached to it. A few games abuse the FDS Disk Data IRQ for frame timing. If bit 7 is set, the FDS RAM adapter will generate IRQs every 1,792 cycles of the 21.4772 MHz master clock, or after every 149+1/3 CPU cycles.
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| ==Cycle IRQ Counter Low Byte ($4100)==
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| This is the low byte of a '''16-bit''' counter that, if nonzero, is increased on every M2 cycle and raises an IRQ when the counter flips from $FFFF to $0000. Writing to this register also acknowledges the IRQ.
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| This register only exists on the ''Bung Super Game Doctor'', not on the original ''Game Doctor'' nor on any models from ''Venus'' and ''Front Fareast''.
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| ==Cycle IRQ Counter High Byte ($4101)==
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| This is the high byte of a '''16-bit''' counter that, if nonzero, is increased on every M2 cycle and raises an IRQ when the counter flips from $FFFF to $0000.
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| =Notes=
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| * [//nesdev.org/mapper6.txt Mapper 6] Info on the FFE mapper. By FanWen Yang (outdated). | | * [//nesdev.org/mapper6.txt Mapper 6] Info on the FFE mapper. By FanWen Yang (outdated). |
| * [http://www.famicomdisksystem.com/game-doctor-copiers/ Info on various Famicom "copiers"] | | * [http://www.famicomdisksystem.com/game-doctor-copiers/ Info on various Famicom "copiers"] |
