CPU variants: Difference between revisions
(Added image of 1818P and UM6557 sourced from https://drive.google.com/drive/folders/1splfmyjpisDjYkXpbjlSoudwbgEAuS1P (Orig. Post: https://forums.nesdev.org/viewtopic.php?t=23682). IDK if T1818P = 1818P, i assumed it to be true) |
(Added some info and added links to the forum posts i used in this (and the previous edit) to the bottom. There are lots more CPU / PPU clones in those threads, but i don't have the time to add them right now.) |
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| UA6527 | | UA6527 | ||
| [[File:CPU=UA6527-8909-BS.jpg|400px]] [[File:CPU=UA6527-9310-CG-C12520.jpg|400px]] | | [[File:CPU=UA6527-8909-BS.jpg|400px]] [[File:CPU=UA6527-9310-CG-C12520.jpg|400px]] | ||
| UMC-made clone of 2A03G. Has swapped pulse channel duty cycles. | | UMC-made clone of 2A03G. Has swapped pulse channel duty cycles. Input clock Divider is 12. | ||
|- | |- | ||
| rowspan=4|UA6527P || colspan=2|UMC-made clone of 2A03G for compatibility with NTSC software in PAL countries. Different input clock divider. Still has swapped pulse channel duty cycles. Otherwise believed same as 6527. | | rowspan=4|UA6527P || colspan=2|UMC-made clone of 2A03G for compatibility with NTSC software in PAL countries. Different input clock divider. Still has swapped pulse channel duty cycles. Otherwise believed same as 6527. | ||
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One revision has (UMC) © Ⓜ B6167F 1989 09 on the die. | One revision has (UMC) © Ⓜ B6167F 1989 09 on the die. | ||
DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. The cause is not known. This changes the timing for [[DMA#Bugs|DMC DMA implicit-stop glitches]] (the sample must be started 1 APU cycle earlier to trigger the glitches), and it is suspected that it delays DMC IRQ by 1 APU cycle. | DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. The cause is not known. This changes the timing for [[DMA#Bugs|DMC DMA implicit-stop glitches]] (the sample must be started 1 APU cycle earlier to trigger the glitches), and it is suspected that it delays DMC IRQ by 1 APU cycle. Noise channel is slightly louder than others. | ||
|- | |- | ||
| [[File:CPU=UA6527P 8931S.jpg|400px]] || Runs hot. Revisions without "-" in the date stamp have a ÷16 CPU divider, like 6540 and 2A07 | | [[File:CPU=UA6527P 8931S.jpg|400px]] || Runs hot. Revisions without "-" in the date stamp have a ÷16 CPU divider, like 6540 and 2A07 | ||
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| [[File:CPU=TA-03N 6527 9250.jpg|400px]] | | [[File:CPU=TA-03N 6527 9250.jpg|400px]] | ||
[[File:CPU=TA-03N 9172N 12450820.jpg|400px]] | [[File:CPU=TA-03N 9172N 12450820.jpg|400px]] | ||
| ??-made die-mask clone of 2A03G. Chip underside also has two codes of currently unknown purpose. Pin 30 activates CPU Test Mode like on 2A03G. Illegal opcodes are the same. Early 1991 dated chips are reported to have problems with APU DMC playback, but this was corrected in 1992 onward. | | ??-made die-mask clone of 2A03G. Chip underside also has two codes of currently unknown purpose. Pin 30 activates CPU Test Mode like on 2A03G. Clock Divisor is 12. Illegal opcodes are the same. Early 1991 dated chips are reported to have problems with APU DMC playback, but this was corrected in 1992 onward. Runs hot. | ||
|- | |- | ||
| TA-03NP | | TA-03NP | ||
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| TA-03NP1 | | TA-03NP1 | ||
| [[File:CPU=TA-03NP1 6527P 9231.jpg|400px]] | | [[File:CPU=TA-03NP1 6527P 9231.jpg|400px]] | ||
| ??-made clone of 2A03G for NTSC compatibility in PAL countries. Input clock divider is 15. Fixed DPCM problems? Correct pulse channel duties. DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. | | ??-made clone of 2A03G for NTSC compatibility in PAL countries. Input clock divider is 15. Fixed DPCM problems? Correct pulse channel duties. Noise channel is slightly louder than others. DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. | ||
|- | |- | ||
| PM03 | | PM03 | ||
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* [[PPU variants]] | * [[PPU variants]] | ||
* https://forums.nesdev.org/viewtopic.php?p=45889#p45889 | * https://forums.nesdev.org/viewtopic.php?p=45889#p45889 | ||
* https://forums.nesdev.org/viewtopic.php?t=23916 (More Info on CPU Clones) | |||
* https://forums.nesdev.org/viewtopic.php?t=23682 (Lots of Images and die-shots) |
Latest revision as of 16:41, 11 October 2024
Beyond the well-studied 2A03G, we know of the following CPU revisions, both made by Ricoh and other manufacturers:
Official (NTSC)
Part | Picture | Notes |
---|---|---|
RP2A03 | M2 duty cycle is 17/24 instead of 15/24 [1]. Lacks tonal noise mode. APU Frame Counter not restarted on reset. Has broken and disabled programmable interval timer on-die. Pin 30 connects to nothing. Other differences? | |
RP2A03E | Pin 30 is /RDY - combined with internal signals before feeding to internal 6502 +RDY. | |
RP2A03G | Reference model. Pin 30 enables a CPU test mode. Later runs introduced a DMC DMA bug [2]. | |
RP2A03H | No known differences from late RP2A03G. | |
RP2A04 | Not actually a CPU at all, just a jumper in a 40-pin PDIP. Used in place of CPUs in Vs. System boards (and thus with NTSC timing). |
Official (PAL)
Part | Picture | Notes |
---|---|---|
RP2A07 | Input clock divider is 16. M2 duty cycle is 19/32 [3]. Changes to noise, DPCM, frame timer tables. Fixed DPCM RDY address bus glitches. Pin 30 connects to 6502 /RDY input. | |
RP2A07A | no known differences relative to 2A07letterless |
Unofficial
Part | Picture | Notes |
---|---|---|
MG-N-501 | ||
MG-P-501 | Micro Genius-made clone. Die has the same (UMC) © Ⓜ B6167F marking as a UA6527P. | |
UA6527 | UMC-made clone of 2A03G. Has swapped pulse channel duty cycles. Input clock Divider is 12. | |
UA6527P | UMC-made clone of 2A03G for compatibility with NTSC software in PAL countries. Different input clock divider. Still has swapped pulse channel duty cycles. Otherwise believed same as 6527.
One revision has (UMC) © Ⓜ B6167F 1989 09 on the die. DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. The cause is not known. This changes the timing for DMC DMA implicit-stop glitches (the sample must be started 1 APU cycle earlier to trigger the glitches), and it is suspected that it delays DMC IRQ by 1 APU cycle. Noise channel is slightly louder than others. | |
Runs hot. Revisions without "-" in the date stamp have a ÷16 CPU divider, like 6540 and 2A07 | ||
Runs hot. Revisions with "-" in the date stamp have a ÷15 CPU divider | ||
Runs cooler | ||
UA6527PQ | ||
UA6540 | UMC-made clone of 2A07 [4]. Has swapped pulse duty cycles.
Subsequent research implies this is identical to the early 6527P - NTSC tuning tables, ÷16 CPU divider. [5] | |
UM6547 | Believed to be a 100% duplicate of UA6527, for use in PAL-M region. | |
UM6557 | Believed to be a 100% duplicate of UA6527, for use in SECAM regions. | |
UM6561xx-1 | No Picture | NES-on-a-chip for NTSC. Revisions "xx" F, AF, BF, CF known. |
UM6561xx-2 | NES-on-a-chip for PAL-B. Revisions "xx" F, AF, BF, CF known.
F and AF revision pulse wave duty cycles match RP2A03, and DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. AF revision observed to have incorrect ASR #imm ($4B) behavior, but other stable illegal instructions work properly. | |
1818N | ??-made NES-on-a-chip, NTSC timing. | |
T1818P | ??-made NES-on-a-chip[[6]. Requires external 2 KiB RAMs for CPU and PPU. Swapped pulse duty cycles. DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. | |
TA-03N | ??-made die-mask clone of 2A03G. Chip underside also has two codes of currently unknown purpose. Pin 30 activates CPU Test Mode like on 2A03G. Clock Divisor is 12. Illegal opcodes are the same. Early 1991 dated chips are reported to have problems with APU DMC playback, but this was corrected in 1992 onward. Runs hot. | |
TA-03NP | ??-made clone of 2A03G for NTSC compatibility in PAL countries. Input clock divider is 15?
But not this one, this input clock divider is 12. | |
TA-03NP1 | ??-made clone of 2A03G for NTSC compatibility in PAL countries. Input clock divider is 15. Fixed DPCM problems? Correct pulse channel duties. Noise channel is slightly louder than others. DMC status bit is cleared 1 APU cycle later than on RP2A03 CPUs. | |
PM03 | Gradiente-made clone of 2A03G. [7] | |
GS870007 | (Goldstar??)-made clone of 2A03 - has functioning decimal mode? [8] | |
KC-6005 | Found in MT777-DX famiclone, behaves exactly like UA6527P | |
6005B | ||
2011 | ||
“2A03E” | Both with and without USC insignia | |
KP2B03E | ||
6527-21 | ||
6527P | ||
HA6527P | ||
6527P-SS-P03 | ||
6527UP-8 | ||
6527AP | ||
SL/WH6527AP | ||
SNC6527P | ||
XYZ-6783 | Lacks tonal noise mode like original RP2A03, but resets APU Frame Counter on console reset like 2A03E/2A03G. Otherwise behaves like letterless RP2A03. | |
6538N | ??-made CPU, despite the part number being similar to UMC PPU. Has inverted duty cycles like UA6527. DPCM works. | |
8Z01N |
If you know of other differences or other revisions, please add them!
See also
- PPU variants
- https://forums.nesdev.org/viewtopic.php?p=45889#p45889
- https://forums.nesdev.org/viewtopic.php?t=23916 (More Info on CPU Clones)
- https://forums.nesdev.org/viewtopic.php?t=23682 (Lots of Images and die-shots)