PPU pinout: Difference between revisions

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(Adds an RGB PPU pinout, makes the page fit the modern formatting a bit better, adds a little more detail.)
 
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[[Category:Pinouts]]
[[Category:Pinouts]]
=== Pin out ===
{{Anchor|Pin out}}
=== Pinout ===
==== Composite PPU ====
Composite PPUs (2C02, 2C07) are the standard PPU in consumer consoles.
           .--\/--.
           .--\/--.
     R/W -> |01  40| -- +5
     R/W -> |01  40| -- +5V
  CPU D0 <> |02  39| -> ALE
  CPU D0 <> |02  39| -> ALE
  CPU D1 <> |03  38| <> PPU AD0
  CPU D1 <> |03  38| <> PPU AD0
Line 20: Line 23:
   EXT3 <> |17  24| -> /RD
   EXT3 <> |17  24| -> /RD
     CLK -> |18  23| -> /WR
     CLK -> |18  23| -> /WR
   /INT <- |19  22| <- /RST
   /INT <+ |19  22| <- /RST
     GND -- |20  21| -> VOUT
     GND -- |20  21| -> VOUT
           `------'
           `------'


=== Signal description ===
==== RGB PPU ====
* R/W, CPU D0-D7, and CPU A0-A2, are signals from the [[CPU pin out and signal description|CPU]]. CPU A2-A0 are tied to the corresponding CPU address pins and select the PPU register (0-7).
RGB PPUs (2C03, 2C04, 2C05) are used mostly in arcade systems. They have the same pinout as composite except that they replace the EXT3..0 and VOUT signals with signals used for RGB video.
* /CS is generated by the [[74139]] (address decoder) on the mainboard to map the PPU regs in the CPU memory range from $2000 to $3FFF.
            ...
**This signal is sometimes referred to as /DBE.
    /CS -> |13  28| -> PPU A10
* EXTx allows the combination of two PPUs - setting the "slave" bit in the [[PPUCTRL]] ($2000) register causes the PPU to output palette indices to these pins, and clearing said bit causes it to instead read indices from these pins (and use them to select the background color).
      '''R''' <- |14  27| -> PPU A11
**For the Vs. System and Playchoice PPUs, EXT0…2 are replaced with R, G, and B respectively. EXT3 is internally and externally tied to ground: perhaps it serves as an analog ground for the video DACs.
      '''G''' <- |15  26| -> PPU A12
* CLK is the 21.47727 MHz (NTSC) or 26.6017 MHz (PAL) clock input. It is doubled for the color generator (and then divided by 12 to get the colorburst frequency) and also divided by 4 (NTSC) or 5 (PAL) for the pixel and memory clocks.
      '''B''' <- |16  25| -> PPU A13
* /INT is an open-drain output, connected to the CPU's /NMI pin as well as a pull-up resistor.
    '''GND''' -- |17  24| -> /RD
* ALE (Address Latch Enable) goes high at the beginning of a PPU VRAM access and is used to latch the lower 8 bits of the PPU's address bus; see the PPU address bus section of [[PPU rendering]]. It stays high for one PPU cycle.
    CLK -> |18  23| -> /WR
* PPU ADx (Address + Data) is the PPU's data bus, multiplexed with the lower 8 bits of the PPU's address bus.
  /INT <+ |19  22| <- /RST
* PPU A8-A13 are the top 6 bits of the PPU's address bus.
    GND -- |20  21| -> '''CSYNC'''
* /RD and /WR specify that the PPU is reading from or writing to VRAM. As an exception, writing to the internal palette range (3F00-3FFF) will not assert /WR.
          `------'
* /RST resets certain parts of the chip to their initial power-on state: the clock divider, video phase generator, scanline/pixel counters, and the even/odd frame toggle. It also keeps several registers zeroed out for a full frame: [[PPUCTRL]], [[PPUMASK]] ($2001), [[PPUSCROLL]] ($2005; the VRAM address latch "T", fine X scroll, and the H/V toggle), and the VRAM read buffer.
 
{{Anchor|Signal description}}
=== Signal descriptions ===
* '''R/W''', '''CPU D7..0''', and '''CPU A2..0''', are signals from the [[CPU pin out and signal description|CPU]]. CPU A2..0 are tied to the corresponding CPU address pins and select the PPU register (0-7).
* '''/CS''' is generated by the [[74139]] (address decoder) on the mainboard to map the PPU regs in the CPU memory range from $2000 to $3FFF.
** This signal is sometimes referred to as /DBE.
* '''EXT3..0''' allows the combination of two PPUs - setting the "slave" bit in the [[PPUCTRL]] ($2000) register causes the PPU to output palette indices to these pins, and clearing said bit causes it to instead read indices from these pins (and use them to select the backdrop color). No official console uses the output mode, so these are normally grounded to set the backdrop to palette entry 0.
** For RGB PPUs, EXT0..2 are replaced with '''R''', '''G''', and '''B''', respectively. EXT3 is internally and externally tied to ground: perhaps it serves as an analog ground for the video DACs.
* '''CLK''' is the 21.47727 MHz (NTSC) or 26.6017 MHz (PAL) clock input. It is doubled for the color generator (and then divided by 12 to get the colorburst frequency) and also divided by 4 (NTSC) or 5 (PAL) for the pixel and memory clocks.
* '''/INT''' is an open-drain output, connected to the CPU's /NMI pin as well as a pull-up resistor.
* '''ALE''' (Address Latch Enable) goes high at the beginning of a PPU VRAM access and is used to latch the lower 8 bits of the PPU's address bus; see the PPU address bus section of [[PPU rendering]]. It stays high for one PPU cycle.
* '''PPU AD7..0''' (Address + Data) is the PPU's data bus, multiplexed with the lower 8 bits of the PPU's address bus.
* '''PPU A13..8''' are the top 6 bits of the PPU's address bus.
* '''/RD''' and '''/WR''' specify that the PPU is reading from or writing to VRAM. As an exception, writing to the internal palette range (3F00-3FFF) will not assert /WR.
* '''/RST''' resets certain parts of the chip to their initial power-on state: the clock divider, video phase generator, scanline/pixel counters, and the even/odd frame toggle. It also keeps several registers zeroed out for a full frame: [[PPUCTRL]], [[PPUMASK]] ($2001), [[PPUSCROLL]] ($2005; the VRAM address latch "T", fine X scroll, and the H/V toggle), and the VRAM read buffer. See [[PPU power up state]].
** This signal is used in the NES to clear the screen when the console is reset either by the button or the [[CIC]].
** This signal is used in the NES to clear the screen when the console is reset either by the button or the [[CIC]].
** Famicom ties this signal directly to the +5V rail, which is why the screen does not clear as you hold down the reset button.
** Famicom ties this signal directly to the +5V rail, which is why the screen does not clear as you hold down the reset button.
** In a dual-PPU system, it can be used to synchronize the "foreground" and "background" PPUs, or it could also be used to [[wikipedia:Genlock|genlock]] multiple independent PPUs together. In either case, care would need to be taken to ensure that the "even/odd frame" state stays consistent between them.
** In a dual-PPU system, it can be used to synchronize the "foreground" and "background" PPUs, or it could also be used to [[wikipedia:Genlock|genlock]] multiple independent PPUs together. In either case, care would need to be taken to ensure that the "even/odd frame" state stays consistent between them.
* VOUT is the [[NTSC_video#Brightness_Levels|shifted analog video]] output. For the Vs. System and Playchoice PPUs, this is only the composite sync signal.
* '''VOUT''' is the [[NTSC_video#Brightness_Levels|shifted analog video]] output.
** For RGB PPUs, this is instead only '''CSYNC''', the composite sync signal.


=== Composite Video Output ===
=== Composite Video Output ===
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  [GND]
  [GND]


The tantalum capacitor reduces a repeating 4 or 8 pixel wide vertical bar artifact.  It is best to specifically use a tantalum centered in the stated range (ex. 10uF), connected ''directly'' from PPU pin 20(-) to 22(+) on the Famicom, or from pin 20(-) to 40(+) on the front-loading NES.  Since this cap is targeting a specific frequency, bigger is not better for this cap -- centered in the range is better.  The existing 2SA937 transistor should be removed to disconnect the RF modulator from the PPU, then reused into this circuit.  Once the 2SA937 is removed, contrary to some online AV mod guides, it has been found conclusively that there is no benefit from cutting any of the PPU's pins or wrapping the PPU in foil. If your original 2SA937 is damaged or lost, you can substitute a common 2N3906, but note that its pinout is different.
The tantalum capacitor reduces a repeating 4 or 8 pixel wide vertical bar artifact.  It is best to specifically use a tantalum centered in the stated range (ex. 10uF), connected ''directly'' from PPU pin 20(-) to 22(+) on the Famicom, or from pin 20(-) to 40(+) on the front-loading NES.  Since this cap is targeting a specific frequency, bigger is not better for this cap -- centered in the range is better.  The existing 2SA937 transistor should be removed to disconnect the RF modulator from the PPU, then reused into this circuit.   
 
On the HVC-CPU(01) through HVC-CPU-08, the NES-CPU-01 through -11, and the NESN-CPU-01, there is no benefit from cutting any of the PPU's pins nor wrapping the PPU in foil.  
 
However, on the HVC-CPU-GPM-01 and -02 boards, isolating pin 21 from its original trace provides a visibly significant improvement.
 
If your original 2SA937 is damaged or lost, you can substitute a common 2N3906, but note that its pinout is different.


   2SA937        2N3906
   2SA937        2N3906
Line 70: Line 94:
=== See also ===
=== See also ===
* [[:File:neswires.jpg|Wiring diagram of RF Famicom]]
* [[:File:neswires.jpg|Wiring diagram of RF Famicom]]
* [http://green.ap.teacup.com/junker/116.html 電子機器(Electronics) Junker's redrawn schematic of the HVC-001]
* [https://archive.is/glr4o Archive of 電子機器(Electronics) Junker's redrawn schematic of the HVC-001] (formerly at green.ap.teacup.com/junker/116.html )
* [http://console5.com/wiki/Nintendo_NES-001#Schematics Electronix Corp's redrawn schematic of the NES-001]
* [http://console5.com/wiki/Nintendo_NES-001#Schematics Electronix Corp's redrawn schematic of the NES-001]
** [https://forums.nesdev.org/viewtopic.php?p=203383#p203383 Fixed errata from page 3 of above schematic]
** [https://forums.nesdev.org/viewtopic.php?p=203383#p203383 Fixed errata from page 3 of above schematic]
== References ==
== References ==
<references />
<references />

Latest revision as of 05:20, 24 May 2024

Pinout

Composite PPU

Composite PPUs (2C02, 2C07) are the standard PPU in consumer consoles. 

          .--\/--.
   R/W -> |01  40| -- +5V
CPU D0 <> |02  39| -> ALE
CPU D1 <> |03  38| <> PPU AD0
CPU D2 <> |04  37| <> PPU AD1
CPU D3 <> |05  36| <> PPU AD2
CPU D4 <> |06  35| <> PPU AD3
CPU D5 <> |07  34| <> PPU AD4
CPU D6 <> |08  33| <> PPU AD5
CPU D7 <> |09  32| <> PPU AD6
CPU A2 -> |10  31| <> PPU AD7
CPU A1 -> |11  30| -> PPU A8
CPU A0 -> |12  29| -> PPU A9
   /CS -> |13  28| -> PPU A10
  EXT0 <> |14  27| -> PPU A11
  EXT1 <> |15  26| -> PPU A12
  EXT2 <> |16  25| -> PPU A13
  EXT3 <> |17  24| -> /RD
   CLK -> |18  23| -> /WR
  /INT <+ |19  22| <- /RST
   GND -- |20  21| -> VOUT
          `------'

RGB PPU

RGB PPUs (2C03, 2C04, 2C05) are used mostly in arcade systems. They have the same pinout as composite except that they replace the EXT3..0 and VOUT signals with signals used for RGB video. 

            ...
   /CS -> |13  28| -> PPU A10
     R <- |14  27| -> PPU A11
     G <- |15  26| -> PPU A12
     B <- |16  25| -> PPU A13
   GND -- |17  24| -> /RD
   CLK -> |18  23| -> /WR
  /INT <+ |19  22| <- /RST
   GND -- |20  21| -> CSYNC
          `------'

Signal descriptions

  • R/W, CPU D7..0, and CPU A2..0, are signals from the CPU. CPU A2..0 are tied to the corresponding CPU address pins and select the PPU register (0-7).
  • /CS is generated by the 74139 (address decoder) on the mainboard to map the PPU regs in the CPU memory range from $2000 to $3FFF.
    • This signal is sometimes referred to as /DBE.
  • EXT3..0 allows the combination of two PPUs - setting the "slave" bit in the PPUCTRL ($2000) register causes the PPU to output palette indices to these pins, and clearing said bit causes it to instead read indices from these pins (and use them to select the backdrop color). No official console uses the output mode, so these are normally grounded to set the backdrop to palette entry 0.
    • For RGB PPUs, EXT0..2 are replaced with R, G, and B, respectively. EXT3 is internally and externally tied to ground: perhaps it serves as an analog ground for the video DACs.
  • CLK is the 21.47727 MHz (NTSC) or 26.6017 MHz (PAL) clock input. It is doubled for the color generator (and then divided by 12 to get the colorburst frequency) and also divided by 4 (NTSC) or 5 (PAL) for the pixel and memory clocks.
  • /INT is an open-drain output, connected to the CPU's /NMI pin as well as a pull-up resistor.
  • ALE (Address Latch Enable) goes high at the beginning of a PPU VRAM access and is used to latch the lower 8 bits of the PPU's address bus; see the PPU address bus section of PPU rendering. It stays high for one PPU cycle.
  • PPU AD7..0 (Address + Data) is the PPU's data bus, multiplexed with the lower 8 bits of the PPU's address bus.
  • PPU A13..8 are the top 6 bits of the PPU's address bus.
  • /RD and /WR specify that the PPU is reading from or writing to VRAM. As an exception, writing to the internal palette range (3F00-3FFF) will not assert /WR.
  • /RST resets certain parts of the chip to their initial power-on state: the clock divider, video phase generator, scanline/pixel counters, and the even/odd frame toggle. It also keeps several registers zeroed out for a full frame: PPUCTRL, PPUMASK ($2001), PPUSCROLL ($2005; the VRAM address latch "T", fine X scroll, and the H/V toggle), and the VRAM read buffer. See PPU power up state.
    • This signal is used in the NES to clear the screen when the console is reset either by the button or the CIC.
    • Famicom ties this signal directly to the +5V rail, which is why the screen does not clear as you hold down the reset button.
    • In a dual-PPU system, it can be used to synchronize the "foreground" and "background" PPUs, or it could also be used to genlock multiple independent PPUs together. In either case, care would need to be taken to ensure that the "even/odd frame" state stays consistent between them.
  • VOUT is the shifted analog video output.
    • For RGB PPUs, this is instead only CSYNC, the composite sync signal.

Composite Video Output

The non-RGB PPUs used in home consoles directly output a shifted analog composite video signal from pin 21. Because of this, it is possible to modify models that only have an RF output to add a composite video output. This is the best-known composite video amplifier circuit[1]: 

[+5V]---------/\/\/-----+
 |            300Ω      |
 |+                     |       +
--- Tantalum            +---------|(---------/\/\/-------+--------+
--- 4.7-47uF           /     Electrolytic    110Ω        |        |   Pin
 |               (b) |L (e)      220uF                   |        +----O } Composite
 |  [PPU.21]---------| PNP                      Ceramic ---              }   Video
 |                   |\ (c) 2SA937                560pF ---       +----O }
 |                     \    (sub: 2N3906)                |        |  Ring
[PPU.20]----------------+--------------------------------+--------+
[GND]

The tantalum capacitor reduces a repeating 4 or 8 pixel wide vertical bar artifact. It is best to specifically use a tantalum centered in the stated range (ex. 10uF), connected directly from PPU pin 20(-) to 22(+) on the Famicom, or from pin 20(-) to 40(+) on the front-loading NES. Since this cap is targeting a specific frequency, bigger is not better for this cap -- centered in the range is better. The existing 2SA937 transistor should be removed to disconnect the RF modulator from the PPU, then reused into this circuit.

On the HVC-CPU(01) through HVC-CPU-08, the NES-CPU-01 through -11, and the NESN-CPU-01, there is no benefit from cutting any of the PPU's pins nor wrapping the PPU in foil.

However, on the HVC-CPU-GPM-01 and -02 boards, isolating pin 21 from its original trace provides a visibly significant improvement.

If your original 2SA937 is damaged or lost, you can substitute a common 2N3906, but note that its pinout is different. 

 2SA937        2N3906
                ___
__ ______      /___\
| V     |      |   |
|_______|      |___|
 |  |  |        /|\
 |  |  |       | | |
 E  C  B       E B C

See also

References

  1. ↑ https://forums.nesdev.org/viewtopic.php?f=9&t=18508
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