File:Palette.jpg: Difference between revisions
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(Palette RAM as physically implemented within the PPU. Note the incomplete address decoding which results in $10/$14/$18/$1C being mirrors of $00/$04/$08/$0C. Also of note, palette RAM bits are significantly larger than those of OAM (which are believed to) |
Rainwarrior (talk | contribs) m (palettes category) |
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Source: http://uxul.org/~noname/chips/rp2c02-0-9g5-14/stitched/ | Source: http://uxul.org/~noname/chips/rp2c02-0-9g5-14/stitched/ | ||
[[Category:Palettes]] | |||
Latest revision as of 01:49, 29 March 2023
Palette RAM as physically implemented within the PPU. Note the incomplete address decoding which results in $10/$14/$18/$1C being mirrors of $00/$04/$08/$0C.
Also of note, palette RAM bits are significantly larger than those of OAM (which are believed to be DRAM).
Source: http://uxul.org/~noname/chips/rp2c02-0-9g5-14/stitched/
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
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| current | 21:56, 21 September 2021 |  | 1,111 × 316 (237 KB) | >Maintenance script | == Summary == Importing file |
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