User talk:Fiskbit: Difference between revisions

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(Add Fiskbit talk page for staging findings.)
 
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I'll be staging information here before finding a place to move it to on the wiki.
== Underlines in plain text ==


== CPU / APU ==
I have to say, I had no idea that you could do underlines within plain text areas like you did in this table, very cool!


=== Behavior ===
  Mode| BG bit depth |Offsets |    Priorities (front -> back)       |                    Notes                      <u>
 
    |BG1 BG2 BG3 BG4|per tile|                                      |                                               
* When the CPU comes out of reset, it is random whether it is aligned on the first or second half of an APU cycle (and thus random whether it begins on a GET or PUT cycle).
  0 | 2  2  2  2 |  No  |  S3 1H 2H S2 1L 2L S1 3H 4H S0 3L 4L|                                                </u>
* The state of the CPU's OUT pins is only updated when transitioning from a GET to PUT cycle. Thus, changes to OUT state lasting only 1 cycle (such as when toggled with an INC instruction) may be missed by the joypad device. This can be used to determine CPU/APU alignment, but poses a problem for expansion port devices that use OUT bits to signal when to snoop the data bus.
  1 | 4  4  2    |  No  |  S3 1H 2H S2 1L 2L S1 3H    S0 3L  |BG3 priority = 0                               <u>
* Readable APU registers ($4015 and, if modded, the test registers) drive the internal CPU bus, but not the external CPU bus, so they do not affect external open bus state. Therefore, a dummy read from one of these registers on the cycle before a read from external open bus (such as by using page crossing on an indexed read) will not change the external open bus value.
    |              |        |3H S3 1H 2H S2 1L 2L S1      S0 3L  |BG3 priority = 1                              
* The CPU clock divider is not affected by reset. Therefore, resetting the CPU preserves CPU/PPU sub-cycle alignment.
  2  | 4  4         | Yes  |  S3 1H    S2 2H    S1 1L    S0 2L  |                                               
 
  3 | 8   4        |  No  |  S3 1H    S2 2H    S1 1L    S0 2L  |                                               
=== Revision differences ===
  4  | 8  2         | Yes  |  S3 1H    S2 2H    S1 1L    S0 2L  |                                               
 
  5  | 4  2        |  No  |  S3 1H    S2 2H    S1 1L    S0 2L  |Fixed 16 pixel char width. Forced high-res mode.
==== Letterless ====
  6 | 4            | Yes  |  S3 1H    S2      S1 1L    S0      |Fixed 16 pixel char width. Forced high-res mode.
 
  7 | 8             |  No  |  S3      S2      S1 1L    S0      |Fixed 8x8 char size.                           </u>
* 4-cycle DMA glitches do not occur.
  7EXT| 8  7         |  No  |  S3      S2 2H    S1 1L    S0 2L  |Fixed 8x8 char size. BG2 bit 7 acts as priority.
* When DMA collides with a joypad read, extra reads occur on each cycle the CPU is halted instead of just one extra read for the whole DMA.
- [[User:Ben Boldt|Ben Boldt]] ([[User talk:Ben Boldt|talk]]) 17:10, 4 May 2022 (UTC)
 
== PPU ==
 
=== Behavior ===
 
* Reads from palette RAM do not set bits 7-6, so these will return PPU open bus.
* Writes to OAM during rendering are ignored.
* The PPU clock divider is affected by reset. Therefore, resetting the PPU changes the CPU/PPU sub-cycle alignment.
 
=== Revision differences ===
 
==== 2C02A ====
 
* Writes to $2001 disrupt rendering similar to toggling it off and on.
* PPU bus write timing differs from later revisions in a way that causes glitches on the Everdrive Pro. (Normal cartridges seem unaffected.)
 
 
== TV-NET ==
 
=== MC-1200 ===
 
  $5000-57FF: CPU/PPU RAM
$6000-6007: Registers (mirrored across $6000-6FFF)
  $7000-7FFF: Cartridge PRG-RAM
$8000-FFFF: Modem/cartridge ROM
 
$6006 appears to control what is mapped into the $5000-57FF window. Observed writes are 4 before writing to what appears to be 1 KB of special graphics memory (MMC5-style ExRAM?) at $5000 and 3 after, and 5 to map in CHR-RAM, which is 32 KB and can be banked using $6002 in 1 KB amounts (unknown if bit 0 ignored).<br />
<br />
When booted without a cartridge inserted, modem ROM is loaded at $8000-FFFF, with unique data at $8000-CFFF and the same 4 KB mirrored across $D000-FFFF. When booted with a cartridge, $8000-DFFF are replaced with cartridge ROM, and $7000-7FFF contains PRG-RAM. The JRA-PAT 3.00 cartridge (blue/green/yellow label) has been found to contain a 256 KB ROM and 32 KB battery-backed RAM. Bankswapping is not yet understood.<br />
<br />
Contents of $8000-FFFF on letterless, A, and B revision modems found to be the same. Included is the string "ROM VERSION A1.0-06.15", suggesting the remaining ROM contents are likely also the same.
 
=== MC-1200 controller ===
 
Covered on the forums [https://forums.nesdev.org/viewtopic.php?t=19878#p248486 here]. Japanese is naively translated with a dictionary. Uses 3 shift registers; every button can be pressed simultaneously.<br />
 
  0 - P/T switch (1 if T)
1 - 終了 (Shuuryou / End)
2  - F3
3  - (Always 1)
4  - F1
5  - F2
6  - F4
7  - F5
  8 - 1
9  - 4
  10 - 7
11 - (Always 1)
12 - 2
  13 - 3
14 - 5
15 - 6
  16 - *
  17 - Left
  18 - 実行 (Jikkou / Run)
19 - Right
20 - 8
21 - 9
22 - 0
23 - .
   
24+ - (Always 1)
 
=== MC-4800 controller ===
 
Included with the TV-NET Rank 2, this controller offers the same functionality as the base TV-NET controller plus 8 additional buttons.<br />
 
0  - P/T switch (1 if T)
1  - • / 実行 (Jikkou / Run)
2  - 後退 (Koutai / Backspace) / F3
3  - (Always 1)
4  - F1
5  - 番組 (Bangumi / Program) / F2
6  - 印字 (Inji / Typing?) / F4
  7 - 取消 (Toke / Cancel) / F5
8  - 1
9  - 4
10 - 7
11 - (Always 1)
12 - 2
13 - 3
14 - 5
15 - 6
16 - *
17 - Left
18 - # / 実行 (Jikkou / Run)
19 - Right
20 - 8
21 - 9
22 - 0
23 - ,
24 - 入力 (Nyuuryoku / Input)
25 - Up
26 - Down
27 - 文字 (Moji / Character)
28 - 機能 (Kinou / Function)
29 - 切替 (Kika / Exchange) / F6
30 - 再送 (Saisou / Resend) / F7
31 - 停再 (Tomasai? / Stop again?) / F8

Latest revision as of 17:10, 4 May 2022

Underlines in plain text

I have to say, I had no idea that you could do underlines within plain text areas like you did in this table, very cool! 

Mode| BG bit depth  |Offsets |     Priorities (front -> back)       |                     Notes                      
    |BG1 BG2 BG3 BG4|per tile|                                      |                                                
 0  | 2   2   2   2 |   No   |   S3 1H 2H S2 1L 2L S1 3H 4H S0 3L 4L|                                                
 1  | 4   4   2     |   No   |   S3 1H 2H S2 1L 2L S1 3H    S0 3L   |BG3 priority = 0                                
    |               |        |3H S3 1H 2H S2 1L 2L S1       S0 3L   |BG3 priority = 1                                
 2  | 4   4         |  Yes   |   S3 1H    S2 2H    S1 1L    S0 2L   |                                                
 3  | 8   4         |   No   |   S3 1H    S2 2H    S1 1L    S0 2L   |                                                
 4  | 8   2         |  Yes   |   S3 1H    S2 2H    S1 1L    S0 2L   |                                                
 5  | 4   2         |   No   |   S3 1H    S2 2H    S1 1L    S0 2L   |Fixed 16 pixel char width. Forced high-res mode.
 6  | 4             |  Yes   |   S3 1H    S2       S1 1L    S0      |Fixed 16 pixel char width. Forced high-res mode.
 7  | 8             |   No   |   S3       S2       S1 1L    S0      |Fixed 8x8 char size.                            
7EXT| 8   7         |   No   |   S3       S2 2H    S1 1L    S0 2L   |Fixed 8x8 char size. BG2 bit 7 acts as priority.

- Ben Boldt (talk) 17:10, 4 May 2022 (UTC)

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