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| [[Category:ASIC mappers]][[Category:Mappers with cycle IRQs]]
| | #REDIRECT [[VRC2 and VRC4]] |
| The Konami VRC4 is an [[:Category:ASIC mappers|ASIC]] [[MMC|mapper]].
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| __TOC__
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| == Overview ==
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| * PRG ROM size: Up to 256 KiB
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| * PRG ROM bank size: 8 KiB at $A000, and $8000 OR $C000
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| * PRG RAM: none, 2 KiB, or 8 KiB
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| * CHR ROM size: Up to 512 KiB
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| * CHR bank size: 1 KiB
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| * Nametable [[mirroring]]: Controlled by mapper
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| * Subject to [[bus conflict]]s: No
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| The Konami VRC4 is almost identical to the [[VRC2|VRC2]], but with a bit more capabilities, such as the option to swap PRG at $C000 instead of $8000 and an IRQ counter.
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| See [[VRC4 pinout]] for chip pinout.
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| == Banks ==
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| * CPU $6000-$6FFF: optional 2 KiB PRG RAM bank (mirrored once), or
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| * CPU $6000-$7FFF: optional 8 KiB PRG RAM bank
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| * CPU $8000-$9FFF (or $C000-$DFFF): 8 KiB switchable PRG ROM bank
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| * CPU $A000-$BFFF: 8 KiB switchable PRG ROM bank
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| * CPU $C000-$DFFF (or $8000-$9FFF): 8 KiB PRG ROM bank, fixed to the second-last bank
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| * CPU $E000-$FFFF: 8 KiB PRG ROM bank, fixed to the last bank
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| * PPU $0000-$03FF: 1 KiB switchable CHR bank
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| * PPU $0400-$07FF: 1 KiB switchable CHR bank
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| * PPU $0800-$0BFF: 1 KiB switchable CHR bank
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| * PPU $0C00-$0FFF: 1 KiB switchable CHR bank
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| * PPU $1000-$13FF: 1 KiB switchable CHR bank
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| * PPU $1400-$17FF: 1 KiB switchable CHR bank
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| * PPU $1800-$1BFF: 1 KiB switchable CHR bank
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| * PPU $1C00-$1FFF: 1 KiB switchable CHR bank
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| == Revisions ==
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| This mapper has been used with several board revisions, each of which uses different address lines.
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| All boards use A15-A12 the same way, along with two lines from A7-A0.
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| Here is a listing of known revisions, which address lines are used, and which [[iNES]] mapper number is used to represent it:
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| variant lines registers iNES Mapper Number
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| ----------------------------------------------------------------------
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| VRC4a A1, A2 $x000, $x002, $x004, $x006 [[INES Mapper 021|021]]
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| VRC4b A1, A0 $x000, $x002, $x001, $x003 025
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| VRC4c A6, A7 $x000, $x040, $x080, $x0C0 021
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| VRC4d A3, A2 $x000, $x008, $x004, $x00C 025
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| VRC4e A2, A3 $x000, $x004, $x008, $x00C 023
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| VRC4 #27 A0, A1 $x000, $x001, $x002, $x003 [[iNES Mapper 027|027]]
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| Some variants that use the same address lines use them in different ways. For example, VRC4d and VRC4e both use A2 and A3, however VRC4d has them reversed.
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| For historical reasons, some variants share a mapper number.
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| These may be detected with a hash of the PRG ROM, or the address lines used may be expressed in NES 2.0 with [[NES 2.0 submappers#VRC4|submappers]].
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| The RAM decoding circuit that's part of the VRC4 itself only decodes RAM from $6000-$6FFF. For the [http://bootgod.dyndns.org:7777/profile.php?id=1573 one game] with 8 KiB of RAM, an external [[PRG RAM circuit|circuit was added]].
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| == Registers ==
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| This page lists registers as they are in the VRC4a variant. For other variants, you can use the diagram above for determining which registers are used.
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| === PRG Swap Mode control ($9004, $9006) ===
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| 7 bit 0
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| ---------
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| .... ..M.
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| +-- Swap Mode
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| When 'M' is clear:
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| * the 8 KiB page at $8000 is controlled by the $800x register
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| * the 8 KiB page at $C000 is fixed to the second last 8 KiB in the ROM
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| When 'M' is set:
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| * the 8 KiB page at $8000 is fixed to the second last 8 KiB in the ROM
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| * the 8 KiB page at $C000 is controlled by the $800x register
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| === PRG Select 0 ($8000, $8002, $8004, $8006) ===
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| 7 bit 0
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| ---------
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| ...P PPPP
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| +-++++- Select 8 KiB PRG bank at $8000 or $C000 depending on Swap Mode
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| === PRG Select 1 ($A000, $A002, $A004, $A006) ===
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| 7 bit 0
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| ---------
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| ...P PPPP
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| +-++++- Select 8 KiB PRG bank at $A000
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| === Mirroring Control ($9000, $9002) ===
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| 7 bit 0
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| ---------
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| .... ..MM
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| ||
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| ++- [[Mirroring]] (0: vertical; 1: horizontal; 2: one-screen, lower bank; 3: one-screen, upper bank)
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| === CHR Select 0 ($B000 + $B002) ===
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| $B000 $B002
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL ...H HHHH
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| |||| | ||||
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| |||| +-++++- High 5 bits of 1 KiB CHR bank at PPU $0000
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| ++++-------------- Low 4 bits
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| === CHR Select 1 ($B004 + $B006) ===
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| $B004 $B006
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| 7 bit 0 7 bit 0
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| --------- ---------
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| .... LLLL ...H HHHH
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| |||| | ||||
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| |||| +-++++- High 5 bits of 1 KiB CHR bank at PPU $0400
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| ++++-------------- Low 4 bits
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| === CHR Select 2…7 ($C000-$EFFF) ===
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| The other six CHR bank selects continue the pattern:
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| {| class="wikitable"
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| ! colspan=2|Write to CPU address
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| |-
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| ! (low 4 bits) !! (high 5 bits) !! 1KB CHR bank affected
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| |-
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| | $C000 || $C002 || $0800-$0BFF
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| |-
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| | $C004 || $C006 || $0C00-$0FFF
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| |-
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| | $D000 || $D002 || $1000-$13FF
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| |-
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| | $D004 || $D006 || $1400-$17FF
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| |-
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| | $E000 || $E002 || $1800-$1BFF
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| |-
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| | $E004 || $E006 || $1C00-$1FFF
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| |}
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| === IRQ Control ($F00x) ===
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| $F000: IRQ Latch, low 4 bits
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| $F002: IRQ Latch, high 4 bits
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| $F004: IRQ Control
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| $F006: IRQ Acknowledge
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| Many VRC mappers use the same IRQ system. For details on IRQ operation, see [[VRC IRQ]]s.
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| == References ==
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| *[http://www.romhacking.net/documents/362/ NES Mapper List] by Disch
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| *[http://nesdev.org/konami-e.txt Konami Mapper] by goroh, translated by Sgt. Bowhack
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| *[http://nesdev.org/mappers.zip Comprehensive NES Mapper Document] by \Firebug\, information about mapper's initial state is inaccurate.
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| * The CHR registers really are 9 bits: http://forums.nesdev.org/viewtopic.php?t=8569
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