CPU: Difference between revisions
From NESdev Wiki
Jump to navigationJump to search
mNo edit summary |
(level 2 headings, cycle ref chart) |
||
| (43 intermediate revisions by 11 users not shown) | |||
| Line 1: | Line 1: | ||
The NES CPU core is based on the 6502 processor and runs at approximately 1.79 MHz (1.66 MHz in a PAL NES). It is made by Ricoh and lacks the MOS6502's decimal mode. In the NTSC NES, the RP2A03 chip contains the CPU and APU; in the PAL NES, the CPU and APU are contained within the RP2A07 chip. | The NES CPU core is based on the 6502 processor and runs at approximately 1.79 MHz (1.66 MHz in a PAL NES). It is made by [http://en.wikipedia.org/wiki/Ricoh Ricoh] and lacks the MOS6502's decimal mode. In the NTSC NES, the [http://en.wikipedia.org/wiki/Ricoh_2A03 RP2A03] chip contains the CPU and APU; in the PAL NES, the CPU and APU are contained within the [http://en.wikipedia.org/wiki/Ricoh_2A03 RP2A07] chip. | ||
== Sections == | |||
* [[6502 instructions|CPU instructions]] | |||
* [[CPU addressing modes]] | |||
* [[CPU memory map]] | |||
* [[CPU power up state|CPU power-up state]] | |||
* [[CPU registers]] | |||
* [[CPU status flag behavior]] | |||
* [[CPU interrupts]] | |||
* [[CPU unofficial opcodes|Unofficial opcodes]] | |||
* [[CPU pinout|CPU pin-out and signals]], and other [[hardware pinout|hardware pin-outs]] | |||
== Frequencies == | |||
The CPU generates its clock signal by dividing the master clock signal. | |||
{| class="tabular" | |||
|- | |||
! Rate || NTSC NES/Famicom || PAL NES || Dendy | |||
|- | |||
| Color subcarrier frequency ''f{{sub|sc}}'' (exact) || 3579545.<span style="text-decoration:overline;">45</span> Hz (315/88 MHz) || 4433618.75 Hz || 4433618.75 Hz | |||
|- | |||
| Color subcarrier frequency ''f{{sub|sc}}'' (approx.) || 3.579545 MHz || 4.433619 MHz || 4.433619 MHz | |||
|- | |||
| Master clock frequency 6''f{{sub|sc}}'' || 21.477272 MHz || 26.601712 MHz || 26.601712 MHz | |||
|- | |||
| Clock divisor ''d'' || 12 || 16 || 15 | |||
|- | |||
| CPU clock frequency 6''f{{sub|sc}}''/''d'' || 1.789773 MHz (~559 ns per cycle) || 1.662607 MHz (~601 ns per cycle) || 1.773448 MHz (~564 ns per cycle) | |||
|} | |||
</ | <nowiki>*</nowiki> The vast majority of PAL famiclones use a chipset or NOAC with this timing. A small number have UMC UA6540+6541, which also uses PAL NES timing.<ref>[https://forums.nesdev.org/viewtopic.php?f=3&t=17213#p216082 nesdev forum: Eugene.S provides a list of famiclones]</ref> | ||
== | == Notes == | ||
* | * All illegal 6502 opcodes execute identically on the 2A03/2A07. | ||
* Every cycle on 6502 is either a read or a write cycle. | |||
* | * A printer friendly version covering all section is available [[CPU ALL|here]]. | ||
* A printer friendly version covering all section is available [[ | * Emulator authors may wish to emulate the NTSC NES/Famicom CPU at 21441960 Hz ((341×262−0.5)×4×60) to ensure a synchronised/stable 60 frames per second.<ref>[http://forums.nesdev.org/viewtopic.php?p=223679#p223679 nesdev forum: Mesen - NES Emulator]</ref> | ||
== See also == | |||
* [[Cycle reference chart]] | |||
* [http://nesdev.org/2A03%20technical%20reference.txt 2A03 technical reference] by Brad Taylor. (Pretty old at this point; information on the wiki might be more up-to-date.) | |||
== References == | |||
<references/> | |||
Latest revision as of 05:35, 11 January 2023
The NES CPU core is based on the 6502 processor and runs at approximately 1.79 MHz (1.66 MHz in a PAL NES). It is made by Ricoh and lacks the MOS6502's decimal mode. In the NTSC NES, the RP2A03 chip contains the CPU and APU; in the PAL NES, the CPU and APU are contained within the RP2A07 chip.
Sections
- CPU instructions
- CPU addressing modes
- CPU memory map
- CPU power-up state
- CPU registers
- CPU status flag behavior
- CPU interrupts
- Unofficial opcodes
- CPU pin-out and signals, and other hardware pin-outs
Frequencies
The CPU generates its clock signal by dividing the master clock signal.
| Rate | NTSC NES/Famicom | PAL NES | Dendy |
|---|---|---|---|
| Color subcarrier frequency fsc (exact) | 3579545.45 Hz (315/88 MHz) | 4433618.75 Hz | 4433618.75 Hz |
| Color subcarrier frequency fsc (approx.) | 3.579545 MHz | 4.433619 MHz | 4.433619 MHz |
| Master clock frequency 6fsc | 21.477272 MHz | 26.601712 MHz | 26.601712 MHz |
| Clock divisor d | 12 | 16 | 15 |
| CPU clock frequency 6fsc/d | 1.789773 MHz (~559 ns per cycle) | 1.662607 MHz (~601 ns per cycle) | 1.773448 MHz (~564 ns per cycle) |
* The vast majority of PAL famiclones use a chipset or NOAC with this timing. A small number have UMC UA6540+6541, which also uses PAL NES timing.[1]
Notes
- All illegal 6502 opcodes execute identically on the 2A03/2A07.
- Every cycle on 6502 is either a read or a write cycle.
- A printer friendly version covering all section is available here.
- Emulator authors may wish to emulate the NTSC NES/Famicom CPU at 21441960 Hz ((341×262−0.5)×4×60) to ensure a synchronised/stable 60 frames per second.[2]
See also
- Cycle reference chart
- 2A03 technical reference by Brad Taylor. (Pretty old at this point; information on the wiki might be more up-to-date.)
