CPROM: Difference between revisions
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[[Category:Discrete_logic_mappers]][[Category:in NesCartDB]] | [[Category:Discrete_logic_mappers]][[Category:in NesCartDB]][[Category:Nintendo licensed mappers]] | ||
NES-[[CPROM]] (no [[Famicom|HVC]]-CPROM known) is a particular Nintendo cartridge board which uses discrete logic to provide up to four 4 KB banks of CHR RAM. | NES-[[CPROM]] (no [[Famicom|HVC]]-CPROM known) is a particular Nintendo cartridge board which uses discrete logic to provide up to four 4 KB banks of CHR RAM. | ||
The [[iNES]] format assigns '''mapper 13''' to this board. | The [[iNES]] format assigns '''mapper 13''' to this board. | ||
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* PRG ROM bank size: Not bankswitched | * PRG ROM bank size: Not bankswitched | ||
* PRG RAM: None | * PRG RAM: None | ||
* CHR capacity: 16 KiB RAM [[Category:Mappers with CHR RAM]] (in two [[6264 static | * CHR capacity: 16 KiB RAM [[Category:Mappers with CHR RAM]] (in two [[6264 static RAM|8KiB RAMs]]) | ||
* CHR bank size: 4 KiB | * CHR bank size: 4 KiB | ||
* Nametable [[mirroring]]: Vertical | * Nametable [[mirroring]]: Vertical | ||
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The CPROM board uses a [[74161|74HC161]] (4-bit latch) and a [[7408|74HC08]] (quad 2-input AND gate), with a [[7404|74HC04]] (hex inverter) to unify the two RAMs. | The CPROM board uses a [[74161|74HC161]] (4-bit latch) and a [[7408|74HC08]] (quad 2-input AND gate), with a [[7404|74HC04]] (hex inverter) to unify the two RAMs. | ||
== See also == | == See also == | ||
* [http://kevtris.org/mappers/nes_discrete/NES_CPROM.html Kevtris's notes] | * [http://kevtris.org/mappers/nes_discrete/NES_CPROM.html Kevtris's notes] | ||
* The [[NROM-368]] proposal is also compatible with this board. | * The [[NROM-368]] proposal is also compatible with this board. | ||
Latest revision as of 22:25, 9 June 2016
NES-CPROM (no HVC-CPROM known) is a particular Nintendo cartridge board which uses discrete logic to provide up to four 4 KB banks of CHR RAM. The iNES format assigns mapper 13 to this board. Only Videomation, a paint program for NES, is known to use it.
Overview
- PRG ROM size: 32 KiB (DIP-28 standard pinout)
- PRG ROM bank size: Not bankswitched
- PRG RAM: None
- CHR capacity: 16 KiB RAM (in two 8KiB RAMs)
- CHR bank size: 4 KiB
- Nametable mirroring: Vertical
- Subject to bus conflicts: Yes
Banks
- PPU $0000-$0FFF: 4 KiB fixed CHR RAM bank (first page)
- PPU $1000-$1FFF: 4 KiB swappable CHR RAM page
Registers
Bank select ($8000-$FFFF)
7 bit 0
---- ----
xxxx xxCC
||
++- Select 4 KiB CHR RAM bank for PPU $1000-$1FFF
Hardware
The CPROM board uses a 74HC161 (4-bit latch) and a 74HC08 (quad 2-input AND gate), with a 74HC04 (hex inverter) to unify the two RAMs.
See also
- Kevtris's notes
- The NROM-368 proposal is also compatible with this board.
