PPU memory map: Difference between revisions

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=== PPU memory map ===
=== PPU memory map ===


The [[PPU]] addresses a 16k space, $0000-3FFF, completely separate from the CPU's data bus. It is either directly accessed by the PPU itself, or via the CPU with [[PPU registers|memory mapped registers]] at $2006 and $2007.
The [[PPU]] addresses a 16kB space, $0000-3FFF, completely separate from the CPU's data bus. It is either directly accessed by the PPU itself, or via the CPU with [[PPU registers|memory mapped registers]] at $2006 and $2007.


The NES has 2k of RAM dedicated to the PPU, normally mapped to the nametable address space from $2000-2FFF, but this can be rerouted through custom cartridge wiring.
The NES has 2kB of RAM dedicated to the PPU, normally mapped to the nametable address space from $2000-2FFF, but this can be rerouted through custom cartridge wiring.


{| class="tabular"
{| class="tabular"
Line 27: Line 27:
|}
|}


In addition, the PPU contains 256 bytes of memory known as [[PPU OAM|Object Attribute Memory]] in a separate address space, which determines how sprites are rendered. The CPU also manipulates this memory through special [[PPU registers|memory mapped registers]] at $2003, $2004, and $4014.
In addition, the PPU internally contains 256 bytes of memory known as [[PPU OAM|Object Attribute Memory]] which determines how sprites are rendered. The CPU can manipulate this memory through special [[PPU registers|memory mapped registers]] at $2003, $2004, and $4014.


{| class="tabular"
{| class="tabular"
! Address range || Size || Description
! Address range || Size || Description
|-
|-
| $00-$0C (0 of 4) || $40 || Sprite Y
| $00-$0C (0 of 4) || $40 || Sprite Y coordinate
|-
|-
| $01-$0D (1 of 4) || $40 || Sprite Tile
| $01-$0D (1 of 4) || $40 || Sprite Tile #
|-
|-
| $02-$0E (2 of 4) || $40 || Sprite Attribute
| $02-$0E (2 of 4) || $40 || Sprite Attribute
|-
|-
| $03-$0F (3 of 4) || $40 || Sprite X
| $03-$0F (3 of 4) || $40 || Sprite X coordinate
|}
|}


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* $0000-1FFF is normally mapped by the cartridge to a [[CHR ROM vs. CHR RAM|CHR-ROM or CHR-RAM]], often with a bank switching mechanism.
* $0000-1FFF is normally mapped by the cartridge to a [[CHR ROM vs. CHR RAM|CHR-ROM or CHR-RAM]], often with a bank switching mechanism.


* $2000-2FFF is normally mapped to the 2k NES internal VRAM, providing 2 nametables with a [[Mirroring#Nametable_Mirroring|mirroring]] configuration controlled by the cartridge, but it can be partly or fully remapped to RAM on the cartridge, allowing up to 4 simultaneous nametables.
* $2000-2FFF is normally mapped to the 2kB NES internal VRAM, providing 2 nametables with a [[Mirroring#Nametable_Mirroring|mirroring]] configuration controlled by the cartridge, but it can be partly or fully remapped to RAM on the cartridge, allowing up to 4 simultaneous nametables.


* $3000-3EFF is usually a mirror of 2k VRAM from $2000-2EFF. The PPU does not render from this address range, so this space has negligible utility.
* $3000-3EFF is usually a mirror of the 2kB region from $2000-2EFF. The PPU does not render from this address range, so this space has negligible utility.


* $3F00-3FFF is not configurable, always mapped to the internal palette control.
* $3F00-3FFF is not configurable, always mapped to the internal palette control.

Revision as of 21:50, 20 January 2015

PPU memory map

The PPU addresses a 16kB space, $0000-3FFF, completely separate from the CPU's data bus. It is either directly accessed by the PPU itself, or via the CPU with memory mapped registers at $2006 and $2007.

The NES has 2kB of RAM dedicated to the PPU, normally mapped to the nametable address space from $2000-2FFF, but this can be rerouted through custom cartridge wiring.

Address range Size Description
$0000-$0FFF $1000 Pattern Table 0 [lower CHR bank]
$1000-$1FFF $1000 Pattern Table 1 [upper CHR bank]
$2000-$23FF $0400 Name Table #0
$2400-$27FF $0400 Name Table #1
$2800-$2BFF $0400 Name Table #2
$2C00-$2FFF $0400 Name Table #3
$3000-$3EFF $0F00 Mirrors of $2000-$2EFF
$3F00-$3F1F $0020 Palette RAM indexes [not RGB values]
$3F20-$3FFF $00E0 Mirrors of $3F00-$3F1F

In addition, the PPU internally contains 256 bytes of memory known as Object Attribute Memory which determines how sprites are rendered. The CPU can manipulate this memory through special memory mapped registers at $2003, $2004, and $4014.

Address range Size Description
$00-$0C (0 of 4) $40 Sprite Y coordinate
$01-$0D (1 of 4) $40 Sprite Tile #
$02-$0E (2 of 4) $40 Sprite Attribute
$03-$0F (3 of 4) $40 Sprite X coordinate

Hardware mapping

The mappings above are the fixed addresses from which the PPU uses to fetch data during rendering. The actual device that the PPU fetches data from, however, may be configured by the cartridge.

  • $0000-1FFF is normally mapped by the cartridge to a CHR-ROM or CHR-RAM, often with a bank switching mechanism.
  • $2000-2FFF is normally mapped to the 2kB NES internal VRAM, providing 2 nametables with a mirroring configuration controlled by the cartridge, but it can be partly or fully remapped to RAM on the cartridge, allowing up to 4 simultaneous nametables.
  • $3000-3EFF is usually a mirror of the 2kB region from $2000-2EFF. The PPU does not render from this address range, so this space has negligible utility.
  • $3F00-3FFF is not configurable, always mapped to the internal palette control.
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