PPU memory map: Difference between revisions
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(Add some clarifying notes and mention OAM as a separately addressed memory space in the PPU.) |
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=== PPU VRAM memory map === | === PPU VRAM (Video RAM) memory map === | ||
The [[PPU]] contains $4000 bytes of Video RAM, laid out as follows in an address space completely separate from the CPU's. | |||
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=== | Code executing in the CPU may read and manipulate the contents of PPU VRAM only indirectly, by using the [[PPU registers]] that are memory-mapped[https://en.wikipedia.org/wiki/Memory-mapped_I/O] to special addresses in [[CPU memory map|CPU address space]]. | ||
In addition, the PPU contains 256 bytes of memory known as [[PPU OAM|Object Attribute Memory]], in a separate address space distinct from that of the VRAM, which determines how sprites are rendered. The CPU also manipulates this memory through special memory-mapped registers in its own address space. | |||
=== VRAM details === | |||
{| class="tabular" | {| class="tabular" | ||
! Address || Size || Note || Description | ! Address || Size || Note || Description | ||
Revision as of 20:37, 19 January 2015
PPU VRAM (Video RAM) memory map
The PPU contains $4000 bytes of Video RAM, laid out as follows in an address space completely separate from the CPU's.
| Address range | Size | Description |
|---|---|---|
| $0000-$0FFF | $1000 | Pattern Table 0 [lower CHR bank] |
| $1000-$1FFF | $1000 | Pattern Table 1 [upper CHR bank] |
| $2000-$23FF | $0400 | Name Table #0 |
| $2400-$27FF | $0400 | Name Table #1 |
| $2800-$2BFF | $0400 | Name Table #2 |
| $2C00-$2FFF | $0400 | Name Table #3 |
| $3000-$3EFF | $0F00 | Mirrors of $2000-$2EFF |
| $3F00-$3F1F | $0020 | Palette RAM indexes [not RGB values] |
| $3F20-$3FFF | $00E0 | Mirrors of $3F00-$3F1F |
Code executing in the CPU may read and manipulate the contents of PPU VRAM only indirectly, by using the PPU registers that are memory-mapped[1] to special addresses in CPU address space.
In addition, the PPU contains 256 bytes of memory known as Object Attribute Memory, in a separate address space distinct from that of the VRAM, which determines how sprites are rendered. The CPU also manipulates this memory through special memory-mapped registers in its own address space.
VRAM details
| Address | Size | Note | Description |
|---|---|---|---|
| $0000 | $1000 | C | Pattern Table #0 |
| $1000 | $1000 | C | Pattern Table #1 |
| $2000 | $03C0 | Name Table #0 | |
| $23C0 | $0040 | Attribute Table #0 | |
| $2400 | $03C0 | N | Name Table #1 |
| $27C0 | $0040 | N | Attribute Table #1 |
| $2800 | $03C0 | N | Name Table #2 |
| $2BC0 | $0040 | N | Attribute Table #2 |
| $2C00 | $03C0 | N | Name Table #3 |
| $2FC0 | $0040 | N | Attribute Table #3 |
| $3000 | $0F00 | R | |
| $3F00 | $0010 | Background palette | |
| $3F10 | $0010 | Sprite palette | |
| $3F20 | $00E0 | P |
- C = This memory is not in the NES but on the cartridge board. It can be CHR ROM or CHR RAM.
- N = Mirrored nametables, in a manner controlled by the cartridge board (see Mirroring)
- P = Palette mirror
- R = Mirror of $2000-2EFF (N)
(Note: All of this, with the exception of the palette, can be rewired in the cartridge. However, their function remains what is listed above even if rewired.)
