Namcot 163 family pinout: Difference between revisions
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(Marked pin 34 as unknown, improved ASCII graphics.) |
(Updated footnote on pin 34. This pin appears as an input. I drove this pin with 100 Hz square wave while writing randomly to registers. I did not observe 100 Hz coming out on any other pin.) |
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| Line 21: | Line 21: | ||
(fr) CPU D7 <> \ 13 0.8mm pitch 36 / <- PPU A12 (f) | (fr) CPU D7 <> \ 13 0.8mm pitch 36 / <- PPU A12 (f) | ||
(fr) CPU D6 <> \ 14 35 / <- PPU A13 (f) | (fr) CPU D6 <> \ 14 35 / <- PPU A13 (f) | ||
(fr) CPU D5 <> \ 15 34 / | (fr) CPU D5 <> \ 15 34 / <- (?) | ||
(fr) CPU D4 <> \ 16 33 / <- PPU /RD (f) or GND (see below) | (fr) CPU D4 <> \ 16 33 / <- PPU /RD (f) or GND (see below) | ||
(fr) CPU D3 <> \ 17 32 / -- +5Vcc | (fr) CPU D3 <> \ 17 32 / -- +5Vcc | ||
| Line 40: | Line 40: | ||
30 Pull-down resistor present on boards with battery for low-power mode | 30 Pull-down resistor present on boards with battery for low-power mode | ||
33 Ground this pin with if CHR's nOE and nCS lines are separate | 33 Ground this pin with if CHR's nOE and nCS lines are separate | ||
34 No function | 34 No known function. This pin behaves as a digital input. Namco PCBs tie this pin to GND. | ||
40 6264 /CE connected to this pin | 40 6264 /CE connected to this pin | ||
44 Might be an enable for CHR RAM. It is a push-pull output reflecting bit 7 in register $F000. | 44 Might be an enable for CHR RAM. It is a push-pull output reflecting bit 7 in register $F000. | ||
Revision as of 01:25, 22 December 2018
The Namcot 129 and 163 seem to be identical. The Namcot 175 and 340 have minor but vital differences.
Namcot 129 and 163: 48-pin QFP (canonically iNES Mapper 019)
_____
/ \
(f) SOUND <- / 1 48 \ -> CHR A14 (r)
(r) CHR A13 <- / 2 47 \ -> CHR A15 (r)
(r) CHR A12 <- / 3 O 46 \ -> CHR A16 (r)
(r) CHR A11 <- / 4 45 \ -> CHR A17 (r)
(fr)*CHR A10 <- / 5 44 \ -> $F000.7
GND -- / 6 43 \ -- +5Vcc
(r) PRG A18 <- / 7 42 \ -> CIRAM /CE (f)
(r) PRG A17 <- / 8 41 \ -> CHR ROM /CE (r)
(r) PRG A16 <- / 9 40 \ -> WRAM /CE (w)
(r) PRG A15 <- / 10 39 \ -> /IRQ (f)
(r) PRG A14 <- / 11 NAMCO 38 \ <- PPU A10 (f)
(r) PRG A13 <- / 12 129/163/175/340 37 \ <- PPU A11 (f)
/ \
\ Package QFP-48, /
(fr) CPU D7 <> \ 13 0.8mm pitch 36 / <- PPU A12 (f)
(fr) CPU D6 <> \ 14 35 / <- PPU A13 (f)
(fr) CPU D5 <> \ 15 34 / <- (?)
(fr) CPU D4 <> \ 16 33 / <- PPU /RD (f) or GND (see below)
(fr) CPU D3 <> \ 17 32 / -- +5Vcc
(fr) CPU D2 <> \ 18 31 / -- GND
+5Vcc -- \ 19 30 / <- M2 (f)
(fr) CPU D1 <> \ 20 29 / <- R/W (fw)
(fr) CPU D0 <> \ 21 28 / <- /ROMSEL (f)
/$E000.7 <- \ 22 27 / <- CPU A14 (f)
(r) PRG /CE <- \ 23 26 / <- CPU A13 (f)
(fr) CPU A11 -> \ 24 25 / <- CPU A12 (fr)
\ /
\ /
\ /
V
05 also connects to CIRAM A10
19,32,43 Some boards connect a battery (through a standard diode switch) to this pin to make the waveform memory nonvolatile
22 This pin is a mysterious open-collector output, reflecting the inverse of bit 7 in register $E000.
30 Pull-down resistor present on boards with battery for low-power mode
33 Ground this pin with if CHR's nOE and nCS lines are separate
34 No known function. This pin behaves as a digital input. Namco PCBs tie this pin to GND.
40 6264 /CE connected to this pin
44 Might be an enable for CHR RAM. It is a push-pull output reflecting bit 7 in register $F000.
(r) - this pin connects to the ROM chips
(f) - this pin connects to the Famicom connector
(w) - this pin connects to the WRAM
Internal Vcc Connections:
19 ------- 43
32 --|>|-- 19/43 (0.7V diode drop)
Powering only 19/43 does not allow any digital operation.
Namcot 175: 48-pin QFP (canonically iNES Mapper 210)
01 sound was removed 05 CIRAM A10 is hardwired to PPU A10 or A11 as appropriate 39 does not provide IRQs 42 does not allow for ROM nametables
Namcot 340: 48-pin QFP (also iNES Mapper 210)
42\ -> ?
41\ -> ?
40\ -> CHR /CE (r)
39\ -> CIRAM A10 (f)
01 sound was also removed.
