NES 2.0 Mapper 534: Difference between revisions

From NESdev Wiki
Jump to navigationJump to search
(Created page with "{{DEFAULTSORT:534}}534534534534 NES 2.0...")
 
(Rewrite based on new dumps)
Line 1: Line 1:
{{DEFAULTSORT:534}}[[Category:Multicart mappers|534]][[Category:Mappers with CHR RAM|534]][[Category:Mappers with scanline IRQs|534]][[Category:MMC3-like mappers|534]]
{{DEFAULTSORT:534}}[[Category:Multicart mappers|534]][[Category:Mappers with CHR RAM|534]][[Category:Mappers with scanline IRQs|534]][[Category:MMC3-like mappers|534]]
NES 2.0 Mapper 534 is used for ''2-in-1 数独/五子棋'' (Sudoku/Gomoku, NJ064) cartridge from Shenzhen Nanjing Technology (深圳市南晶). It uses an [[MMC3]] clone with additional circuitry for changing the MMC3's two fixed banks. Pattern tables are stored in 8 KiB of unbanked CHR-RAM.
'''NES 2.0 Mapper 534''' denotes an MMC3-based multicart mapper with an optional (G)NROM-like mode.
* ''Atari Flashback Mini 7800''
* ''2-in-1 数独/五子棋'' (NJ064) by Shenzhen Nanjing
* ''18-in-1 Educational Computer'' by Zhuhai S.E.Z. Liming Electronic Co. Ltd.
* ''8-in-1'' (kk3311) by Waixing
* ''8-in-1'' (kk3314) by Waixing


==MMC3-compatible registers ($8000-$FFFF, write)==
==MMC3-compatible registers ($8000-$FFFF, write)==
These registers function identically to a normal [[MMC3]], except in NROM mode.
These registers function identically to a normal [[MMC3]], except that the scanline counter latch register ($C000) takes the ''inverted'' value (XOR $FF) compared to a regular MMC3.


==NROM Register ($6000, write)==
==Outer Bank/PRG Mask Register ($6800, write)==
  Mask: probably $E003
  Mask: $E803
   
   
  D~7654 3210
  D~7654 3210
   ---------
   ---------
   .N.. ...P
   .N.C CPPp
     |     +- PRG A14 mode if N=1
     | | |||+- PRG A17 if N=1
     |         0: PRG-ROM A14=CPU A14 (NROM-256)
     | | |++-- PRG A19..A18
     |         1: PRG-ROM A14=1 (NROM-128)
     | +-+---- CHR A17..A18
     +-------- NROM mode
     +-------- PRG A17 mode
               0: disabled: PRG-ROM connected normally to MMC3
               0: PRG A17=MMC3 PRG A17 (256 KiB inner PRG bank)
               1: enabled: MMC3 CPU A14 input held low;
               1: PRG A17=p (128 KiB inner PRG bank)
                  PRG-ROM A14 subject to "p" bit


If N=1, the two MMC3 bank registers 6 and 7 specify PRG-ROM's A15-A17 (i.e. the 32 KiB bank) for both CPU $8000-$BFFF and $C000-$FFFF, and the 16 KiB bank in that range is determined by the P bit: If P=0, the 16 KiB bank bit is substituted with CPU address bit 14 to form one 32 KiB bank similar to NROM-256. If P=1, the 16 KiB bank bit is held high to create two mirrored 16 KiB banks. NROM mode requires MMC3 bank registers 6 and 7 specify two continuous 8 KiB banks and PRG A14 inversion in MMC3 register $8000 bit 6 to be disabled.
==Solder Pad Register ($6801, write)==
==CHR-RAM Register ($6003, write)==
  Mask: $E803
  Mask: probably $E003
   
   
  D~7654 3210
  D~7654 3210
   ---------
   ---------
   L..P ....
   .... ...M
  |  +------ CHR-RAM write-protect
          +- 0: CPU $8000-$FFFF reads PRG-ROM
  |          0=disabled, CHR-RAM write-enabled
              1: CPU $8000-$FFFF reads solder pad (D0/D1)
  |          1=enabled, CHR-RAM write-protected
  +--------- Lock extra registers
              0=disabled, can write to $6000/$6003
              1=enabled, writes to $6000/$6003 ignored until next reset


==Inner CHR Bank Register ($6802, write)==
Mask: $E803
D~7654 3210
  ---------
  .... CCCC
        ++++- CHR A16..A13 in GNROM mode,
              ignored otherwise
MMC3's CHR A10..A12 still apply, and therefore should be set up to form a contiguous 8 KiB bank.
==Mode Register ($6803, write)==
Mask: $E803
D~7654 3210
  ---------
  L..M ??N.
  |  |  +-- PRG A14 mode if L=1
  |  |        0: PRG A14=MMC3 PRG A14 (NROM-128)
  |  |        1: PRG A14=CPU A14 (NROM-256)
  |  +------ Banking mode
  |          0: MMC3 banking
  |          1: GNROM banking
  +--------- Lock registers $6800 and $6803
As was the case with [[NES 2.0 Mapper 373|similar mappers]], GNROM banking is implemented by holding MMC3 clone's CPU A14 input is low, so that MMC3 registers #6 and #7 apply both to $8000/$C000 and $A000/$E000, and replacing the MMC3's PRG A14 with CPU A14 in NROM-256 mode (N=1).
==Note==
==Note==
* The NROM and CHR registers function as a substitute for WRAM and can only be written to if $A001 bit 7 is set and $A001 bit 6 is clear.
* Outer bank registers overlay any WRAM, and can only be written to if WRAM is enabled in the MMC3 ($A001=$80).
* There may be registers at $6001 and $6002 as well, but the only game using this mapper does not access them.
* Register $6802 is not affected by the Lock bit in register $6803.

Revision as of 21:36, 12 February 2020

NES 2.0 Mapper 534 denotes an MMC3-based multicart mapper with an optional (G)NROM-like mode.

  • Atari Flashback Mini 7800
  • 2-in-1 数独/五子棋 (NJ064) by Shenzhen Nanjing
  • 18-in-1 Educational Computer by Zhuhai S.E.Z. Liming Electronic Co. Ltd.
  • 8-in-1 (kk3311) by Waixing
  • 8-in-1 (kk3314) by Waixing

MMC3-compatible registers ($8000-$FFFF, write)

These registers function identically to a normal MMC3, except that the scanline counter latch register ($C000) takes the inverted value (XOR $FF) compared to a regular MMC3.

Outer Bank/PRG Mask Register ($6800, write)

Mask: $E803

D~7654 3210
  ---------
  .N.C CPPp
   | | |||+- PRG A17 if N=1
   | | |++-- PRG A19..A18
   | +-+---- CHR A17..A18
   +-------- PRG A17 mode
              0: PRG A17=MMC3 PRG A17 (256 KiB inner PRG bank)
              1: PRG A17=p (128 KiB inner PRG bank)

Solder Pad Register ($6801, write)

Mask: $E803

D~7654 3210
  ---------
  .... ...M
          +- 0: CPU $8000-$FFFF reads PRG-ROM
             1: CPU $8000-$FFFF reads solder pad (D0/D1)

Inner CHR Bank Register ($6802, write)

Mask: $E803

D~7654 3210
  ---------
  .... CCCC
       ++++- CHR A16..A13 in GNROM mode,
             ignored otherwise

MMC3's CHR A10..A12 still apply, and therefore should be set up to form a contiguous 8 KiB bank.

Mode Register ($6803, write)

Mask: $E803

D~7654 3210
  ---------
  L..M ??N.
  |  |   +-- PRG A14 mode if L=1
  |  |        0: PRG A14=MMC3 PRG A14 (NROM-128)
  |  |        1: PRG A14=CPU A14 (NROM-256)
  |  +------ Banking mode
  |           0: MMC3 banking
  |           1: GNROM banking
  +--------- Lock registers $6800 and $6803

As was the case with similar mappers, GNROM banking is implemented by holding MMC3 clone's CPU A14 input is low, so that MMC3 registers #6 and #7 apply both to $8000/$C000 and $A000/$E000, and replacing the MMC3's PRG A14 with CPU A14 in NROM-256 mode (N=1).

Note

  • Outer bank registers overlay any WRAM, and can only be written to if WRAM is enabled in the MMC3 ($A001=$80).
  • Register $6802 is not affected by the Lock bit in register $6803.
Retrieved from "https://www.nesdev.org/w/index.php?title=NES_2.0_Mapper_534&oldid=8139"