NES 2.0 Mapper 391: Difference between revisions
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{{DEFAULTSORT:391}}[[Category:Multicart mappers]][[Category:MMC3-like mappers]][[Category:Mappers with scanline IRQs]] | {{DEFAULTSORT:391}}[[Category:Multicart mappers]][[Category:MMC3-like mappers]][[Category:Mappers with scanline IRQs]] | ||
'''NES 2.0 Mapper 391''' denotes the MMC3-based '''BS-110''' PCB. It is a variation of [[INES Mapper 052]] that adds support for GNROM-like PRG bankswitching. Note that the UNIF MAPR '''BMC-BS-110''' is | '''NES 2.0 Mapper 391''' denotes the MMC3-based '''BS-110''' PCB. It is a variation of [[INES Mapper 052]] that adds support for GNROM-like PRG bankswitching. Note that the UNIF MAPR '''BMC-BS-110''' is incorrectly-named and refers to [[NES 2.0 Mapper 444]] instead. | ||
==Outer Bank Register ($6000-$7FFF, write)== | ==Outer Bank Register ($6000-$7FFF, write)== | ||
Latest revision as of 19:36, 8 September 2021
NES 2.0 Mapper 391 denotes the MMC3-based BS-110 PCB. It is a variation of INES Mapper 052 that adds support for GNROM-like PRG bankswitching. Note that the UNIF MAPR BMC-BS-110 is incorrectly-named and refers to NES 2.0 Mapper 444 instead.
Outer Bank Register ($6000-$7FFF, write)
Mask: $E000
A~FEDC BA98 7654 3210 D~7654 3210
------------------- ---------
011. ...C .... .... LcGC pNPP
| |||| ||++- PRG A17..A18
| |||| |+--- NROM mode type if G=1
| |||| | 0=NROM-128
| |||| | 1=NROM-256
| |||| +---- Outer PRG bank size
| |||| 0=256 KiB (PRG A17 from MMC3)
| |||| 1=128 KiB (PRG A17 from outer bank register)
| |||+------ CHR A17
| ||+------- PRG banking mode
| || 0=MMC3 PRG banking mode
| || 1=GNROM-like PRG banking mode
| |+-------- Outer CHR bank size
| | 0=256 KiB (CHR A17 from MMC3) |
| | 1=128 KiB (CHR A17 from outer bank register)
| +--------- 1=Lock outer bank register
+------------------------ CHR A18
GNROM mode means that:
- the MMC3's CPU A14 input is held low, so MMC3 registers 6 and 7 apply to both $8000/$A000 and $C000/$E000,
- in NROM-256 mode, PRG A14 is additionally replaced with CPU A14.
As it uses the MMC3 clones's WRAM interface, writing to the outer bank register requires enabling and not write-protecting WRAM in the MMC's $A001 register.
MMC3-compatible registers ($8000-$FFFF)
Mask: $E001 See MMC3.
