Aladdin deck enhancer pinout: Difference between revisions

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(Created page with "Category:pinouts +------+ NC |01 36| VCC NC |02 35| INNER2 INNER3 |03 34| INNER1 NC |04 33| ROM /OE NC |05 32| ROM /CE A0 |06 31|...")
 
(replaced the inner/outer location with proper register names to eliminate disambiguities)
Line 1: Line 1:
[[Category:pinouts]]
[[Category:pinouts]]


        +------+
                  Deck | CART | Deck
NC     |01  36| VCC
                        ------  
NC     |02  35| INNER2
                NC   |01  36| -- +5V
  INNER3 |03  34| INNER1
                NC   |02  35| <- $C000.2 OR CPU A14
NC     |04  33| ROM /OE
  $C000.3 OR CPU A14 -> |03  34| <- $C000.1 OR CPU A14
NC     |05  32| ROM /CE
                NC   |04  33| <- ROM /OE
A0     |06  31| D0
                NC   |05  32| <- ROM /CE
A1     |07  30| D1
            CPU A0 -> |06  31| -> CPU D0
A2     |08  29| D2
            CPU A1 -> |07  30| -> CPU D1
A3     |09  28| D3
            CPU A2 -> |08  29| -> CPU D2
A4     |10  27| D4
            CPU A3 -> |09  28| -> CPU D3
A5     |11  26| D5
            CPU A4 -> |10  27| -> CPU D4
A6     |12  25| D6
            CPU A5 -> |11  26| -> CPU D5
A7     |13  24| D7
            CPU A6 -> |12  25| -> CPU D6
A8     |14  23| INNER0
            CPU A7 -> |13  24| -> CPU D7
A9     |15  22| A13
            CPU A8 -> |14  23| <- $C000.0 OR CPU A14
A10   |16  21| A12
            CPU A9 -> |15  22| <- CPU A13
A11   |17  20| OUTER0
            CPU A10 -> |16  21| <- CPU A12
GND   |18  19| OUTER1
            CPU A11 -> |17  20| <- $8000.4
        +------+
                GND -- |18  19| <- $8000.3
  ^             
                        ------  
  +------------- label side (01 = leftmost)
                2x18 pin 0.1" edge connector
       
                           
2x18 pin 0.1" edge connector
Notes:
* Pins 01-18 are on the label side (01 = lefmost)
INNER0=$C000.0 (OR CPU A14)
* ROM /OE is logically (not CPU R/W) or CPU /ROMSEL
INNER1=$C000.1 (OR CPU A14)
* ROM /CE is grounded in Aladdin Deck Enhancer 1.1 and driven by PIC16C54 in 2.0
INNER2=$C000.2 (OR CPU A14)
* Single game cartridges wire ROM as: PRG A17 = $C000.3, PRG A16 = $C000.2, PRG A15 = $C000.1, PRG A14 = $C000.0
INNER3=$C000.3 (OR CPU A14)
* Quattro cartridges wire wire ROM as: PRG A17 = $8000.3, PRG A16 = $8000.4, PRG A15 = $C000.1, PRG A14 = $C000.0
OUTER0=$8000.4
OUTER1=$8000.3


* Source: [http://forums.nesdev.org/viewtopic.php?f=9&t=19781&p=273471#p273471]
Source:
* BBS: [http://forums.nesdev.org/viewtopic.php?f=9&t=19781&p=273471#p273471]

Revision as of 14:07, 3 June 2021


                 Deck | CART | Deck
                       ------ 
                NC    |01  36| -- +5V
                NC    |02  35| <- $C000.2 OR CPU A14
$C000.3 OR CPU A14 -> |03  34| <- $C000.1 OR CPU A14
                NC    |04  33| <- ROM /OE
                NC    |05  32| <- ROM /CE
            CPU A0 -> |06  31| -> CPU D0
            CPU A1 -> |07  30| -> CPU D1
            CPU A2 -> |08  29| -> CPU D2
            CPU A3 -> |09  28| -> CPU D3
            CPU A4 -> |10  27| -> CPU D4
            CPU A5 -> |11  26| -> CPU D5
            CPU A6 -> |12  25| -> CPU D6
            CPU A7 -> |13  24| -> CPU D7
            CPU A8 -> |14  23| <- $C000.0 OR CPU A14
            CPU A9 -> |15  22| <- CPU A13
           CPU A10 -> |16  21| <- CPU A12
           CPU A11 -> |17  20| <- $8000.4
               GND -- |18  19| <- $8000.3
                       ------ 
               2x18 pin 0.1" edge connector

Notes:

  • Pins 01-18 are on the label side (01 = lefmost)
  • ROM /OE is logically (not CPU R/W) or CPU /ROMSEL
  • ROM /CE is grounded in Aladdin Deck Enhancer 1.1 and driven by PIC16C54 in 2.0
  • Single game cartridges wire ROM as: PRG A17 = $C000.3, PRG A16 = $C000.2, PRG A15 = $C000.1, PRG A14 = $C000.0
  • Quattro cartridges wire wire ROM as: PRG A17 = $8000.3, PRG A16 = $8000.4, PRG A15 = $C000.1, PRG A14 = $C000.0

Source:

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