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| [[Category:iNES Mappers|090]] | | #REDIRECT [[J.Y. Company ASIC]] |
| Here are Disch's original notes:
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| ========================
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| = Mapper 090 =
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| = + 209 =
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| ========================
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|
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| aka
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| --------------------------
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| Tekken 2 Pirate Cart
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| a big fat pile of ass
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|
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|
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| Example Games:
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| --------------------------
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| Tekken 2 (090)
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| Mortal Kombat 2 (090)
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| Super Contra 3 (090)
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| Super Mario World (090)
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| Shin Samurai Spirits 2 (209)
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|
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|
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| Rants:
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| ---------------------------
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| This mapper is such a big pain in the ass. Not only is it overly complicated in every possible way, but
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| every single game that uses it SUCKS. Plus the composers for these horrible pirate games must have been
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| tone-deaf, because the music is always out of key. I freaking hate this mapper with a passion (can you
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| tell?).
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|
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|
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| 090 vs. 209
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| ---------------------------
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| 209 split from 090 somewhere along the line... but at some time, 090 was shared by both. Therefore you may
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| come across ROMs mislabelled as 090 that are actually 209.
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|
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| The two mappers are exactly the same. The only difference is a jumper setting which controls the extended
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| nametable control. 090 has extended NT control permanently disabled, 209 has it enabled. Why this is in a
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| jumper setting I don't know... since the game can already freaking enable/disable the mode through software!
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| Regardless... two mappers are needed because some games that don't use the NT control don't disable it
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| through software (they rely on the jumper setting disabling it).
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|
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| This doc, as a whole, applies to both 090 and 209 -- with the exception of the Mirroring section, which draws
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| the distinctions between the two.
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|
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|
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| Notes:
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| ---------------------------
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| This mapper has no PRG-RAM. As suprising as that is.
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|
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| In addition to the above mentioned jumper setting that controls mirroring, there are 2 other dipswitch
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| settings which can be read back by the game via reg $5000. Changing the dipswitch can change the game being
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| played in some ROMs (really, it's more or less the same game, just with slight differences).
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|
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|
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| This document's organization:
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| ---------------------------
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| Since there are so many registers for this mapper, registers will be listed and outlined as the features are
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| explained... and the overall registers section will be extremely brief -- serving primarily as a very quick
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| reference or checklist.
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|
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|
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|
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| PRG Setup:
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| ---------------------------
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|
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| $8000-8003 are PRG regs. $8004-8007 are mirrors of them.
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| $8000-$8003: [.PPP PPPP]
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|
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| $D000 is the PRG mode select (among other things):
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| $D000: [SRNC CPPP]
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| R,N = Relate to Mirroring (see mirroring section for details)
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| C = Relate to CHR Setup (see chr setup for details)
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| S = Put PRG @ $6000-7FFF
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| P = PRG Mode Select
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|
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| If 'S' is clear, $6000-7FFF is always open bus. It is only when 'S' is set, that $6000 reflects the page
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| indicated in the setup chart below.
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|
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| Notice that page numbers are "actual" pages.
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|
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| Some modes are bit reversed (as marked below). This means that the PRG registers are to be interpretted
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| backwards:
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|
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| [.ABC DEFG] normal order
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| [.GFE DCBA] bit reversed order
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|
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|
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| $6000 $8000 $A000 $C000 $E000
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| +-----------------+-------------------------------+
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| PRG Mode %000 | ($8003 * 4)+3 | { -1} |
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| +-----------------+-------------------------------+
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| PRG Mode %001 | ($8003 * 2)+1 | $8001 | { -1} |
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| +-----------------+---------------+---------------+
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| PRG Mode %010 | $8003 | $8000 | $8001 | $8002 | { -1} |
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| +-----------------+-------+-------+-------+-------+
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| PRG Mode %011 | $8003 | $8000 | $8001 | $8002 | { -1} | *BIT REVERSE*
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| +-----------------+-------------------------------+
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| PRG Mode %100 | ($8003 * 4)+3 | $8003 |
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| +-----------------+-------------------------------+
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| PRG Mode %101 | ($8003 * 2)+1 | $8001 | $8003 |
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| +-----------------+---------------+---------------+
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| PRG Mode %110 | $8003 | $8000 | $8001 | $8002 | $8003 |
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| +-----------------+-------+-------+-------+-------+
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| PRG Mode %111 | $8003 | $8000 | $8001 | $8002 | $8003 | *BIT REVERSE*
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| +-----------------+-------+-------+-------+-------+
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|
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|
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| In case you don't see the patterns:
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| - PRG modes %1xx are the same as %0xx, only $8003 is used for the last page instead of {-1}
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| - $6000 is always swapped to the last 8k in the block specified by $8003. In %1xx modes, this means $6000
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| will always mirror $E000.
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|
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|
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| CHR Setup:
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| ---------------------------
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|
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| $9000-9007 are CHR regs -- each specifies the low 8 bits of the CHR page
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| $A000-A007 -- specifies the high 8 bits of the CHR page (work with above regs)
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|
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| The rest of this section refers to above regs as $900x only -- but note that it all includes $900x and $A00x.
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|
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| CHR Mode is set by the following:
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|
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| $D000: [SRNC CPPP]
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| R,N = Relate to Mirroring (see mirroring section for details)
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| S,P = Relate to PRG (see prg setup for details)
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| C = CHR Mode
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|
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| $ : [M.BH HHHH]
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| M = Mirror CHR (very strange, see below)
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| B = CHR Block mode (0=enabled, 1=disabled)
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| H = CHR Block (when in block mode)
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|
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|
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| In CHR Block mode ('B' clear), $A00x is ignored, and instead, the H bits selects a 256k block for all CHR.
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| $9000-9007 select a page within that block.
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|
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| In normal mode ('B' set), $9000-9007 select a page from the entire CHR.
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|
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| Mirror CHR mode ('M' set), only takes effect when in 1k or 2k mode ('C' = %10 or %11). In this mode,
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| $0800-$0FFF always mirrors $0000-07FF. ($1800 is unaffected, however). This is relatively easily
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| emulatable by using $9000+$9001 in place of $9002+$9003 in the chart below.
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|
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| Note that page numbers are in "actual" pages.
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|
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| $0000 $0400 $0800 $0C00 $1000 $1400 $1800 $1C00
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| +---------------------------------------------------------------+
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| CHR Mode %00: | $9000 |
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| +---------------------------------------------------------------+
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| CHR Mode %01: | $9000 | $9004 |
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| +-------------------------------+-------------------------------+
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| CHR Mode %10: | $9000 | $9002 | $9004 | $9006 |
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| +---------------+---------------+---------------+---------------+
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| CHR Mode %11: | $9000 | $9001 | $9002 | $9003 | $9004 | $9005 | $9006 | $9007 |
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| +-------+-------+-------+-------+-------+-------+-------+-------+
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|
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|
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|
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| Mirroring:
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| ---------------------------
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|
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| At first glance... mirroring appears simple:
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|
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| $D001: [.... ..MM]
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| %00 = Vert
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| %01 = Horz
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| %10 = 1ScA
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| %11 = 1ScB
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|
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| However there is a special setting to complicate this, of course.
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|
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| Note! For mapper 090, the above is it! None of the below special mirroring stuff applies. The below
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| mirroring info applies *only* to mapper 209.
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|
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|
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| $D000: [SRNC CPPP]
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| S,P = Relate to PRG (see prg setup for details)
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| C = Relates to CHR (see chr setup for details)
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| N = Enable advanced NT control (0=disabled, 1=enabled)
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| R = disable NT RAM (0=NT can be RAM or ROM, 1=NT ROM only)
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|
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| When 'N' is clear, $D001 controls mirroring, and all other mirroring regs are ignored (including 'R' bit of
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| $D000). When 'N' is set, $D001 is ignored, and the below regs control mirroring.
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|
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|
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| $D002: [A... ....] NT RAM select bit
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| $B000-B003 NT Regs (low 8 bits)
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| $B004-B007 NT Regs (high 8 bits)
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|
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| Just like with normal CHR Regs, NT CHR regs are 16-bits... $B000-B003 specify the low bits, and $B004-B007
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| specify the high bit. They are arranged in the following:
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|
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| [ $B000 ][ $B001 ]
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| [ $B002 ][ $B003 ]
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|
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| When 'R' is set, $D002 is ignored, and CHR-ROM is always used as NT (with page selected by appropriate reg).
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| When 'R' is clear... CHR-ROM is only used if bit 7 of the NT Reg does not match the 'A' bit of $D002. If the
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| bits match, then NES internal NT RAM is used instead (either NTA or NTB, depending on bit 0 of the NT reg)
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|
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|
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|
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| IRQs
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| ---------------------------
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|
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| IRQs on this mapper are 100% completely insane. They decided to do everything possible in order to make IRQs
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| as obfuscated and ridiculous as possible.
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|
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| IRQs are triggered by any one of 4 sources:
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| 1) CPU Cycles
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| 2) A12 Rises
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| 3) PPU Reads (wtf, I know, but it's true)
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| 4) CPU Writes (wtf, I know, but it's true)
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|
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| I *think* the only method used by any games is the A12. CPU Cycles may also be used... and I really doubt
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| the other two are used anywhere.
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|
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| A12 rises operate just like they do for MMC3 (mapper 004 -- see that doc for details). One key difference:
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| Unlike the MMC3, nearby rises are not ignored. This means that under "normal" conditions, this IRQ counter
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| is clocked 8 times per scanline (not just once).
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|
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| Clocks are first run through a prescaler, which divides the clocks by either 256 or 8 (prescaling by 8 is
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| useful with A12 mode).
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|
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| Also.. the counter can be configured to count up, or count down! Among other oddities.
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|
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| Related regs are as follows:
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|
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| $C001: [DU.. FPSS]
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| D = Count-down mode (0=disabled, 1=enabled)
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| U = Count-up mode (0=disabled, 1=enabled)
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| F = Funky mode (0=disabled, 1=enabled) -- see below
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| P = Prescaler size (0=256, 1=8)
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| S = IRQ source:
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| %00 = CPU Cycles
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| %01 = PPU A12 rising edges
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| %10 = PPU Reads
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| %11 = CPU Writes
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|
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|
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| $C002: [.... ....] Any write here will acknowledge and disable IRQs
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| $C003: [.... ....] Any write here will enable IRQs
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| $C000: [.... ...E] Alternate method:
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| writing to this reg with E=0: same as writing to $C002
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| writing to this reg with E=1: same as writing to $C003
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|
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| $C004: [PPPP PPPP] Prescaler. Any write here will set the prescaler to 'P' XOR $C006
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| $C005: [IIII IIII] IRQ Counter. Any write here will set the IRQ counter to 'I' XOR $C006
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| $C006: [XXXX XXXX] This value is used as a XOR when writing to $C004/5
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|
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| $C007: Funky Mode Reg
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|
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|
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|
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| $C004 and $C005 directly change the IRQ counter/prescaler. They do not change a reload value.
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|
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| When Count-up and count-down mode are both enabled, or both disabled, the IRQ counter will stand still. Only
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| one can be enabled for IRQs to work.
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|
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| When the prescaler is in 3-bit mode (divide by 8), the high 5 bits of the prescaler remain unchanged when
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| clocked and only the low 3 bits are used. When the low 3 bits wrap, the IRQ counter is clocked. 8-bit mode
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| (divide by 256) works as you'd expect.
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|
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| When the IRQ counter wraps (either $FF->00 or $00->FF, depending on whether it's incrementing or
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| decrementing), an IRQ is tripped (if enabled).
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|
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| Disabling IRQs does not stop the counter or prescaler from counting, it simply stops the IRQ from being
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| generated.
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|
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|
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|
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| Funky Mode:
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|
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| When 'F' in $C001 is clear, $C007 is ignored. When set, exact operation is unknown. It appears to funkify
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| the prescaler. $C007 containing any value other than $FF will result in the IRQ counter not being clocked at
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| all... and $FF will result in the prescaler dividing by strange amounts (sometimes 8? sometimes 12?
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| sometimes 257?). Details are unknown. Fortunately, no games use this funky mode.
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|
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|
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| Other crap:
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| ---------------------------
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|
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| $5000: [DD.. ....] Dipswitch settings (readable only)
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| These bits can be read back as any value depending on dipswitch settings on the cart. The high bit, in
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| paticular, has an effect in some games.
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|
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|
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| $5800, $5801: 8*8->16 multiplication reg. (read+write)
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| These are similar to MMC5's multiplication reg. You write two values you want multiplied to $5801 and
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| $5800, then the 16-bit product can be read back ($5800 has low 8 bits, $5801 has high 8 bits).
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| Mulitplication is unsigned. Multiplication appears to need some processing time. After writing values, wait
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| 8 CPU cycles before reading.
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|
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| $5803: a single byte of RAM (read+write)
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|
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|
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| $5804-$5807 may also be RAM -- it's unknown.
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|
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|
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|
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| Registers:
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| ---------------------------
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| Registers were all covered in detail in previous sections. This section is just an overall
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| reference/checklist.
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|
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|
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|
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| Range, Mask: $5000-FFFF, $F007
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|
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|
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| $5000: Dipswitch (read only)
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| $5800-5801: 8*8->16 multiplier (read+write)
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| $5803: RAM (read+write)
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| $5804-5807: ??? (possibly RAM)
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|
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| $8000-8003: PRG Regs
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| $8004-8007: Mirror of PRG Regs
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|
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| $9000-9007: CHR Regs (low bits)
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| $A000-A007: CHR Regs (high bits)
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|
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| $B000-B003: NT Regs (low bits)
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| $B004-B007: NT Regs (high bits)
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|
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| $C000-C007: IRQ Regs
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|
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| $D000- : Control/Mode Regs
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| $D004-D007: mirror $D000-
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