APU Status: Difference between revisions
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[[Category:APU]] | |||
The [[APU|NES APU]] status register allows channels to be enabled and disabled, and the current playing status of channels and the interrupt flags to be read. | The [[APU|NES APU]] status register allows channels to be enabled and disabled, and the current playing status of channels and the interrupt flags to be read. | ||
Revision as of 20:02, 26 May 2012
The NES APU status register allows channels to be enabled and disabled, and the current playing status of channels and the interrupt flags to be read.
| $4015 | ---D.NT21 | NES APU Status (write) |
| bit 4 | ---D ---- | If clear, the DMC's bytes remaining is set to 0, otherwise the DMC sample is restarted only if the DMC's bytes remaining is 0. |
| bit 3 | ---- N--- | Noise channel's length counter enabled flag |
| bit 2 | ---- -T-- | Triangle channel's length counter enabled flag |
| bit 1 | ---- --2- | Pulse channel 2's length counter enabled flag |
| bit 0 | ---- ---1 | Pulse channel 1's length counter enabled flag |
| Side effects | After the write, the DMC's interrupt flag is cleared, any length counter that is disabled is reset to 0. | |
| $4015 | IF-D.NT21 | NES APU Status (read) |
| bit 7 | I--- ---- | DMC interrupt flag |
| bit 6 | -F-- ---- | Frame interrupt flag |
| bit 4 | ---D ---- | DMC bytes remaining is non-zero |
| bit 3 | ---- N--- | Noise channel's length counter is non-zero |
| bit 2 | ---- -T-- | Triangle channel's length counter is non-zero |
| bit 1 | ---- --2- | Pulse channel 2's length counter is non-zero |
| bit 0 | ---- ---1 | Pulse channel 1's length counter is non-zero |
| Side effects | Clears the frame interrupt flag after being read (but not the DMC interrupt flag). If an interrupt flag was set at the same moment of the read, it will read back as 1 but it will not be cleared. | |
