INES Mapper 118: Difference between revisions
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== Registers == | == Registers == | ||
The behavior of these boards differs from that of a typical MMC3 board in the use of the upper CHR address line. | The behavior of these boards differs from that of a typical MMC3 board in the use of the upper CHR address line. | ||
This board rely on the fact that the MMC3 ignores A13 and page name table adress with 1k/2k banks like it does to bankswitch CHR. This has normally no effect, because the CHR ROM/RAM is disabled during nametable fetches. | This board rely on the fact that the MMC3 ignores A13 and page name table adress with 1k/2k banks like it does to bankswitch CHR. This has normally no effect, because the CHR ROM/RAM is disabled during nametable fetches. | ||
Revision as of 04:26, 13 June 2009
iNES Mapper 118 is used to designate TKSROM and TLSROM boards, both of which use the Nintendo MMC3 in a nonstandard way. The only known difference between these boards and TKROM and TLROM is the mirroring configuration. The CHR A16 line connects directly to CIRAM A10 line instead of MMC3's CIRAM A10 output, to compensate for the MMC3's lack of single-screen mirroring.
Registers
The behavior of these boards differs from that of a typical MMC3 board in the use of the upper CHR address line. This board rely on the fact that the MMC3 ignores A13 and page name table adress with 1k/2k banks like it does to bankswitch CHR. This has normally no effect, because the CHR ROM/RAM is disabled during nametable fetches.
However, on these particular boards, the CHR bankswitching dirrectly affects the mirroring mapping the nametable RAM in either two 2KB banks (allowing only single-screen or horizontal mirroring) or four 1KB banks (allowing all mirroring modes one can think of, because this is equal to the size of a nametable) at the only price of mapping the 1KB CHR banks to the first pattern table by setting bit 7 of $8000. (if the IRQ counter is being used in a standard way, this involve having sprites bankswitched by 2 KB banks and background with 1 KB banks).
Bank data ($8001-$9FFF, odd)
7 bit 0 ---- ---- MDDD DDDD |||| |||| |+++-++++- New bank value, based on last value written to Bank select register | 0: Select 2 KB CHR bank at PPU $0000-$07FF (or $1000-$17FF); | 1: Select 2 KB CHR bank at PPU $0800-$0FFF (or $1800-$1FFF); | 2: Select 1 KB CHR bank at PPU $1000-$13FF (or $0000-$03FF); | 3: Select 1 KB CHR bank at PPU $1400-$17FF (or $0400-$07FF); | 4: Select 1 KB CHR bank at PPU $1800-$1BFF (or $0800-$0BFF); | 5: Select 1 KB CHR bank at PPU $1C00-$1FFF (or $0C00-$0FFF); | 6, 7: as standard MMC3 | +--------- Mirroring configuration, based on the last value written to Bank select register 0: Select Nametable at PPU $2000-$27FF 1: Select Nametable at PPU $2800-$2FFF Note : Those bits are ignored if corresponding CHR banks are mapped at $1000-$1FFF via $8000. 2 : Select Nametable at PPU $2000-$23FF 3 : Select Nametable at PPU $2400-$27FF 4 : Select Nametable at PPU $2800-$2BFF 5 : Select Nametable at PPU $2C00-$2FFF Note : Those bits are ignored if corresponding CHR banks are mapped at $1000-$1FFF via $8000.
Mirroring ($A000-$BFFE, even)
7 bit 0
---- ----
xxxx xxxM
|
+- Mirroring
This bit is bypassed by the configuration described above, so writing here has no effect.
Note: In theory, the CHR limitation is 256 KB like all MMC3 boards. But because CHR A16 has another usage, having a CHR greater than 128 KB would require very careful CHR ROM layout because CHR bankswitching and mirroring will be linked through the same selection bits. For instance, a game using 1-screen mirroring could draw the playfield with the lower 128 KB of CHR ROM and the lower nametable, and draw the status bar and menus with the upper 128 KB of CHR ROM and the upper nametable.
