INES Mapper 017

iNES Mapper 017 is used for ROM images that have been converted from disk images for or the native file format of the Front Fareast Super Magic Card RAM cartridge.

Banks (in game mode)

• CPU $5000-$5FFF: 4 KiB scratch RAM bank, fixed
• CPU $6000-$7FFF: 8 KiB WRAM bank, switchable via register $4500 from 32 KiB total
• CPU $8000-$9FFF: 8 KiB PRG-ROM bank, switchable via register $4504 from 512 KiB total
• CPU $A000-$BFFF: 8 KiB PRG-ROM bank, switchable via register $4505 from 512 KiB total
• CPU $C000-$DFFF: 8 KiB PRG-ROM bank, switchable via register $4506 from 512 KiB total
• CPU $E000-$FFFF: 8 KiB PRG-ROM bank, switchable via register $4507 from 512 KiB total
• PPU $0000-$03FF: 1 KiB CHR-RAM bank, switchable via register $4510 from 256 KiB total
• PPU $0400-$07FF: 1 KiB CHR-RAM bank, switchable via register $4511 from 256 KiB total
• PPU $0800-$0BFF: 1 KiB CHR-RAM bank, switchable via register $4512 from 256 KiB total
• PPU $0C00-$0FFF: 1 KiB CHR-RAM bank, switchable via register $4513 from 256 KiB total
• PPU $1000-$13FF: 1 KiB CHR-RAM bank, switchable via register $4514 from 256 KiB total
• PPU $1400-$17FF: 1 KiB CHR-RAM bank, switchable via register $4515 from 256 KiB total
• PPU $1800-$1BFF: 1 KiB CHR-RAM bank, switchable via register $4516 from 256 KiB total
• PPU $1C00-$1FFF: 1 KiB CHR-RAM bank, switchable via register $4517 from 256 KiB total
• PPU $2000-$23FF: 1 KiB CIRAM or CHR-RAM bank, CHR-RAM bank switchable via register $4518 from 256 KiB total
• PPU $2400-$27FF: 1 KiB CIRAM or CHR-RAM bank, CHR-RAM bank switchable via register $4519 from 256 KiB total
• PPU $2800-$2BFF: 1 KiB CIRAM or CHR-RAM bank, CHR-RAM bank switchable via register $451A from 256 KiB total
• PPU $2C00-$2FFF: 1 KiB CIRAM or CHR-RAM bank, CHR-RAM bank switchable via register $451B from 256 KiB total

Registers

PRG-"ROM" Write-protection/Mirroring ($42FC-$42FF, write)

A~FEDC BA98 7654 3210  D~7654 3210
  -------------------    ---------
  0100 0010 1111 11PM    ...M ....
                   |+-------+------ Set nametable mirroring type
                   |                (if CIRAM is enabled)
                   |                 0: One-screen, page 0
                   |                 1: One-screen, page 1
                   |                 2: Vertical
                   |                 3: Horizontal
                   +--------------- PRG-"ROM" write-protection
                                     0: disabled, PRG-"ROM" write-enabled
                                     1: enabled, PRG-"ROM" write-protected

Configuration Register ($4500, write)

D~7654 3210
  ---------
  PMWW ImNC
  |||| |||+- CHR-RAM mode
  |||| |||    0: Game-Doctor-compatible mode, do not use $4510-$4517
  |||| |||    1: Super Magic Card mode, use $4510-$4517
  |||| ||+-- Nametable mode
  |||| ||     0: CHR-RAM, use $4518-$451C
  |||| ||     1: CIRAM, mirrored according to $42FC-$42FF
  |||| |+--- MMC4-like Latch in Super Magic Card CHR-RAM mode
  |||| |      0: Enabled (ignored when C=0)
  |||| |      1: Disabled
  |||| +---- IRQ source select
  ||||        0: M2 rise
  ||||        1: PA12 rise (unfiltered, e.g. 8 rises per scanline)
  ||++------ Select 8 KiB WRAM bank at CPU $6000-$7FFF
  |+-------- Select memory map
  |           0: GUI/Load: $6000-$BFFF: PRG-"ROM"/WRAM
  |                        $C000-$FFFF: BIOS
  |           1: Game: $6000-$7FFF: WRAM
  |                    $8000-$FFFF: PRG-"ROM"
  +--------- Pass-through mode
              0: Disabled, show GUI or play game from PRG-"ROM"
              1: Enabled, play cartrige inserted into SMC's cartridge connector

IRQ Disable ($4501, write)

Acknowledges IRQ and disables counting.

IRQ Counter Low Byte ($4502, write)

This is the low byte of a 15-bit (D0-D14) counter that, if nonzero, is increased on every M2/PA12 rise and raises an IRQ when the counter flips from $7FFF to $0000. Writing to this register also acknowledges the IRQ.

IRQ Counter High Byte ($4503, write)

This is the high byte of a 15-bit (D0-D14) counter that, if nonzero, is increased on every M2/PA12 rise and raises an IRQ when the counter flips from $7FFF to $0000. Writing to this register also acknowledges the IRQ and enables counting.

PRG-"ROM" Bank registers ($4504-$4507, write)

• $4504: Set 8 KiB PRG-"ROM" bank at CPU $8000-$9FFF
• $4505: Set 8 KiB PRG-"ROM" bank at CPU $A000-$BFFF
• $4506: Set 8 KiB PRG-"ROM" bank at CPU $C000-$DFFF
• $4507: Set 8 KiB PRG-"ROM" bank at CPU $E000-$FFFF. Hard reset default: last bank.

CHR-RAM Bank registers ($4510-$451B, write)

• $4510: Set 1 KiB CHR-RAM bank at PPU $0000-$03FF
• $4511: Set 1 KiB CHR-RAM bank at PPU $0400-$07FF
• $4512: Set 1 KiB CHR-RAM bank at PPU $0800-$0BFF
• $4513: Set 1 KiB CHR-RAM bank at PPU $0C00-$0FFF
• $4514: Set 1 KiB CHR-RAM bank at PPU $1000-$13FF
• $4515: Set 1 KiB CHR-RAM bank at PPU $1400-$17FF
• $4516: Set 1 KiB CHR-RAM bank at PPU $1800-$1BFF
• $4517: Set 1 KiB CHR-RAM bank at PPU $1C00-$1FFF
• $4518: Set 1 KiB CHR-RAM bank at PPU $2000-$23FF if $4500.1=0
• $4519: Set 1 KiB CHR-RAM bank at PPU $2400-$27FF if $4500.1=0
• $451A: Set 1 KiB CHR-RAM bank at PPU $2800-$2BFF if $4500.1=0
• $451B: Set 1 KiB CHR-RAM bank at PPU $2C00-$2FFF if $4500.1=0

If the MMC4-like latch is enabled ($4500.0=1 and $4500.2=0), the meaning of these registers differs:

• $4510/$4511, D3-D7: Set 4 KiB CHR-RAM bank at PPU $0000-$0FFF when latch=0
• $4512/$4513, D3-D7: Set 4 KiB CHR-RAM bank at PPU $0000-$0FFF when latch=1
• $4514/$4515, D3-D7: Set 4 KiB CHR-RAM bank at PPU $1000-$1FFF when latch=0
• $4516/$4517, D3-D7: Set 4 KiB CHR-RAM bank at PPU $1000-$1FFF when latch=1
• PPU A10 still selects between even and odd registers, so both should receive the same value.
• As on the Nintendo MMC4, the latch is set to 0 when the PPU reads from $0FD8-$0FDF/$1FD8-$1FDF and to 1 when the PPU reads from $0FE8-$0FEF/$1FE8-$1FEF.

Notes

• 512-byte Trainers are loaded and initialized by JMP/JSRing to an address specified by the header of the SMC's native file format. iNES format files lack this information. Heuristically, battery-backup games load and JMP to $5D00, non-battery games with CHR-ROM load and JMP to $7000, while CHR-ROM-less games load to $7000 and JSR to $7003 before JMPing to ($FFFC).
• BIOS changes every game's NMI vector to a routine at $5032 that checks whether the unit's real-time save button has been pressed before passing control to the game's original NMI handler. As a result, M2-based IRQs set up in that handler will occur 75 M2 cycles later than normally.