INES Mapper 017: Difference between revisions

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(This thing can do CHR-RAM nametables.)
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[[Category:INES Mappers|017]][[Category:Mappers with cycle IRQs]][[Category:Mappers with scanline IRQs]]
[[Category:INES Mappers|017]][[Category:Mappers with cycle IRQs]][[Category:Mappers with scanline IRQs]]
iNES Mapper 017 is used for ROM images that have been converted from disk images for the ''Front FarEast Super Magic Card'' copiers. All of these ROM images have been modified to use the copier's idiosyncratic bankswitch registers.
iNES Mapper 017 is used for ROM images that have been converted from disk images for or the native file format of the ''Front Fareast Super Magicard'' RAM cartridges.


Unlike the ''[[INES Mapper 006|Bung Game Doctor]]'', the Super Magic Card has 256 KiB of CHR-RAM, allowing an entire game's CHR-ROM to fit. This drastically reduces the amount of modification necessary. Still, many of these images contain a 512-byte trainer that is loaded into PRG-RAM at $7000 if the game does not use battery-backed RAM, otherwise the trainer is loaded to $5D00 to not interfere with the save data.
=Banks (in game mode)=
 
* CPU $5000-$5FFF: 4 KiB scratch RAM bank, fixed
=Banks=
* CPU $6000-$7FFF: 8 KiB WRAM bank, switchable via register $4500 from 32 KiB total
* CPU $8000-$9FFF: 8 KiB PRG-ROM bank, switchable via register $4504
* CPU $8000-$9FFF: 8 KiB PRG-ROM bank, switchable via register $4504 from 512 KiB total
* CPU $A000-$BFFF: 8 KiB PRG-ROM bank, switchable via register $4505
* CPU $A000-$BFFF: 8 KiB PRG-ROM bank, switchable via register $4505 from 512 KiB total
* CPU $C000-$DFFF: 8 KiB PRG-ROM bank, switchable via register $4506
* CPU $C000-$DFFF: 8 KiB PRG-ROM bank, switchable via register $4506 from 512 KiB total
* CPU $E000-$FFFF: 8 KiB PRG-ROM bank, switchable via register $4507
* CPU $E000-$FFFF: 8 KiB PRG-ROM bank, switchable via register $4507 from 512 KiB total
* PPU $0000-$03FF: 1 KiB CHR-RAM bank, switchable via register $4510
* PPU $0000-$03FF: 1 KiB CHR-RAM bank, switchable via register $4510 from 256 KiB total
* PPU $0400-$07FF: 1 KiB CHR-RAM bank, switchable via register $4511
* PPU $0400-$07FF: 1 KiB CHR-RAM bank, switchable via register $4511 from 256 KiB total
* PPU $0800-$0BFF: 1 KiB CHR-RAM bank, switchable via register $4512
* PPU $0800-$0BFF: 1 KiB CHR-RAM bank, switchable via register $4512 from 256 KiB total
* PPU $0C00-$0FFF: 1 KiB CHR-RAM bank, switchable via register $4513
* PPU $0C00-$0FFF: 1 KiB CHR-RAM bank, switchable via register $4513 from 256 KiB total
* PPU $1000-$13FF: 1 KiB CHR-RAM bank, switchable via register $4514
* PPU $1000-$13FF: 1 KiB CHR-RAM bank, switchable via register $4514 from 256 KiB total
* PPU $1400-$17FF: 1 KiB CHR-RAM bank, switchable via register $4515
* PPU $1400-$17FF: 1 KiB CHR-RAM bank, switchable via register $4515 from 256 KiB total
* PPU $1800-$1BFF: 1 KiB CHR-RAM bank, switchable via register $4516
* PPU $1800-$1BFF: 1 KiB CHR-RAM bank, switchable via register $4516 from 256 KiB total
* PPU $1C00-$1FFF: 1 KiB CHR-RAM bank, switchable via register $4517
* PPU $1C00-$1FFF: 1 KiB CHR-RAM bank, switchable via register $4517 from 256 KiB total
* PPU $2000-$23FF: 1 KiB CIRAM or CHR-RAM bank, CHR-RAM bank switchable via register $4518 from 256 KiB total
* PPU $2400-$27FF: 1 KiB CIRAM or CHR-RAM bank, CHR-RAM bank switchable via register $4519 from 256 KiB total
* PPU $2800-$2BFF: 1 KiB CIRAM or CHR-RAM bank, CHR-RAM bank switchable via register $451A from 256 KiB total
* PPU $2C00-$2FFF: 1 KiB CIRAM or CHR-RAM bank, CHR-RAM bank switchable via register $451B from 256 KiB total


=Registers=
=Registers=
==Mirroring ($42FC-$42FF)==
==PRG-"ROM" Write-protection/Mirroring ($42FC-$42FF, write)==
  A~FEDC BA98 7654 3210  D~7654 3210
  A~FEDC BA98 7654 3210  D~7654 3210
   -------------------    ---------
   -------------------    ---------
   0100 0010 1111 11.M   ...M ....
   0100 0010 1111 11PM   ...M ....
                    +-------+------ Set nametable mirroring type
                    |+-------+------ Set nametable mirroring type
                                      0: One-screen, page 0
                    |                (if CIRAM is enabled)
                                      1: One-screen, page 1
                    |                0: One-screen, page 0
                                      2: Vertical
                    |                1: One-screen, page 1
                                      3: Horizontal
                    |                2: Vertical
                    |                3: Horizontal
                    +--------------- PRG-"ROM" write-protection
                                      0: disabled, PRG-"ROM" write-enabled
                                      1: enabled, PRG-"ROM" write-protected


==Copier Configuration Register ($4500)==
==Configuration Register ($4500, write)==
  D~7654 3210
  D~7654 3210
   ---------
   ---------
   MMWW IPPP
   PMWW IcNC
   |||| |+++- PPU Mode. Set by the copier BIOS, games assume it to be 7.
   |||| |||+- CHR-RAM mode
  |||| |||    0: Game-Doctor-compatible mode, do not use $4510-$4517
  |||| |||    1: Super Magicard mode, use $4510-$4517
  |||| ||+-- Nametable mode
  |||| ||    0: CHR-RAM, use $4518-$451C
  |||| ||    1: CIRAM, mirrored according to $42FC-$42FF
  |||| |+--- Must be identical to C
   |||| +---- IRQ source select
   |||| +---- IRQ source select
   ||||        0: M2 rise
   ||||        0: M2 rise
   ||||        1: PA12 rise (unfiltered, e.g. 8 rises per scanline)
   ||||        1: PA12 rise (unfiltered, e.g. 8 rises per scanline)
   ||++------ SRAM mode at $6000-$7FFF. Set by the copier BIOS, games assume it to be 0.
   ||++------ Select 8 KiB WRAM bank at CPU $6000-$7FFF
   ++-------- Copier mode. Set by the copier BIOS, games assume it to be 1.
  |+-------- Select memory map
  |          0: GUI/Load: $6000-$BFFF: PRG-"ROM"/WRAM
  |                        $C000-$FFFF: BIOS
  |          1: Game: $6000-$7FFF: WRAM
  |                    $8000-$FFFF: PRG-"ROM"
   +--------- Pass-through mode
              0: Disabled, show GUI or play game from PRG-"ROM"
              1: Enabled, play cartrige inserted into SMC's cartridge connector


==IRQ Disable ($4501)==
==IRQ Disable ($4501, write)==
Acknowledges and disables the IRQ counter.
Acknowledges IRQ and disables counting.


==IRQ Counter Low Byte ($4502)==
==IRQ Counter Low Byte ($4502, write)==
This is the low byte of a '''15-bit''' (D0-D14) counter that, if nonzero, is increased on every M2/PA12 rise and raises an IRQ when the counter flips from $7FFF to $0000. Writing
This is the low byte of a '''15-bit''' (D0-D14) counter that, if nonzero, is increased on every M2/PA12 rise and raises an IRQ when the counter flips from $7FFF to $0000. Writing to this register also acknowledges the IRQ.
to this register also acknowledges the IRQ.


==IRQ Counter High Byte ($4503)==
==IRQ Counter High Byte ($4503, write)==
This is the high byte of a '''15-bit''' (D0-D14) counter that, if nonzero, is increased on every M2/PA12 rise and raises an IRQ when the counter flips from $7FFF to $0000. Writing
This is the high byte of a '''15-bit''' (D0-D14) counter that, if nonzero, is increased on every M2/PA12 rise and raises an IRQ when the counter flips from $7FFF to $0000. Writing to this register also acknowledges the IRQ and enables counting.
to this register also acknowledges and enables the IRQ.


==PRG-ROM Bank registers ($4504-$4507)==
==PRG-"ROM" Bank registers ($4504-$4507, write)==
* $4504: Set 8 KiB PRG-ROM bank at CPU $8000-$9FFF
* $4504: Set 8 KiB PRG-"ROM" bank at CPU $8000-$9FFF
* $4505: Set 8 KiB PRG-ROM bank at CPU $A000-$BFFF
* $4505: Set 8 KiB PRG-"ROM" bank at CPU $A000-$BFFF
* $4506: Set 8 KiB PRG-ROM bank at CPU $C000-$DFFF
* $4506: Set 8 KiB PRG-"ROM" bank at CPU $C000-$DFFF
* $4507: Set 8 KiB PRG-ROM bank at CPU $E000-$FFFF
* $4507: Set 8 KiB PRG-"ROM" bank at CPU $E000-$FFFF. Hard reset default: last bank.


==CHR-RAM Bank registers ($4510-$4517)==
==CHR-RAM Bank registers ($4510-$451B, write)==
* $4510: Set 1 KiB CHR-RAM bank at PPU $0000-$03FF
* $4510: Set 1 KiB CHR-RAM bank at PPU $0000-$03FF
* $4511: Set 1 KiB CHR-RAM bank at PPU $0400-$07FF
* $4511: Set 1 KiB CHR-RAM bank at PPU $0400-$07FF
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* $4516: Set 1 KiB CHR-RAM bank at PPU $1800-$1BFF
* $4516: Set 1 KiB CHR-RAM bank at PPU $1800-$1BFF
* $4517: Set 1 KiB CHR-RAM bank at PPU $1C00-$1FFF
* $4517: Set 1 KiB CHR-RAM bank at PPU $1C00-$1FFF
* $4518: Set 1 KiB CHR-RAM bank at PPU $2000-$23FF if $4500.1=0
* $4519: Set 1 KiB CHR-RAM bank at PPU $2400-$27FF if $4500.1=0
* $451A: Set 1 KiB CHR-RAM bank at PPU $2800-$2BFF if $4500.1=0
* $451B: Set 1 KiB CHR-RAM bank at PPU $2C00-$2FFF if $4500.1=0


=Notes=
=Notes=
* Before control is transferred to the game's Reset handler vectored at $FFFC, the copier BIOS issues a JSR to the Trainer's Init routine, if present. This call is necessary to properly set up initial CHR-RAM content and bankswitching registers. A few games also set up a table with IRQ counter values. Unlike [[INES Mapper 006]], the location of this Init routine varies between games. If a game has battery-backed RAM, this Init routine is always at $5D00; otherwise it can be at either $7000 or $7003, with the correct one detectable only via heuristics. $7003 seems to be correct unless the value at $7000 is $6C (indicating an indirect JMP), or both $7000 and $7003 contain the value $4C (JMP) ''and'' the jump offset at $7001 is lower than the jump offset at $7004.
* 512-byte Trainers are loaded and initialized by JMP/JSRing to an address specified by the header of the SMC's native file format. iNES format files lack this information. Heuristically, battery-backup games load and JMP to $5D00, non-battery games with CHR-ROM load and JMP to $7000, while CHR-ROM-less games load to $7000 and JSR to $7003 before JMPing to ($FFFC).
* The FFE hack of ''Doki! Doki! Yuenchi'' has a graphical glitch during the introduction: the audience moves horizontally, caused by the IRQ handler writing an uninitialized Y register to $2005 that should be zero.
* BIOS changes every game's NMI vector to a routine at $5032 that checks whether the unit's real-time save button has been pressed before passing control to the game's original NMI handler. As a result, M2-based IRQs set up in that handler will occur 75 M2 cycles later than normally.

Revision as of 20:58, 30 March 2019

iNES Mapper 017 is used for ROM images that have been converted from disk images for or the native file format of the Front Fareast Super Magicard RAM cartridges.

Banks (in game mode)

  • CPU $5000-$5FFF: 4 KiB scratch RAM bank, fixed
  • CPU $6000-$7FFF: 8 KiB WRAM bank, switchable via register $4500 from 32 KiB total
  • CPU $8000-$9FFF: 8 KiB PRG-ROM bank, switchable via register $4504 from 512 KiB total
  • CPU $A000-$BFFF: 8 KiB PRG-ROM bank, switchable via register $4505 from 512 KiB total
  • CPU $C000-$DFFF: 8 KiB PRG-ROM bank, switchable via register $4506 from 512 KiB total
  • CPU $E000-$FFFF: 8 KiB PRG-ROM bank, switchable via register $4507 from 512 KiB total
  • PPU $0000-$03FF: 1 KiB CHR-RAM bank, switchable via register $4510 from 256 KiB total
  • PPU $0400-$07FF: 1 KiB CHR-RAM bank, switchable via register $4511 from 256 KiB total
  • PPU $0800-$0BFF: 1 KiB CHR-RAM bank, switchable via register $4512 from 256 KiB total
  • PPU $0C00-$0FFF: 1 KiB CHR-RAM bank, switchable via register $4513 from 256 KiB total
  • PPU $1000-$13FF: 1 KiB CHR-RAM bank, switchable via register $4514 from 256 KiB total
  • PPU $1400-$17FF: 1 KiB CHR-RAM bank, switchable via register $4515 from 256 KiB total
  • PPU $1800-$1BFF: 1 KiB CHR-RAM bank, switchable via register $4516 from 256 KiB total
  • PPU $1C00-$1FFF: 1 KiB CHR-RAM bank, switchable via register $4517 from 256 KiB total
  • PPU $2000-$23FF: 1 KiB CIRAM or CHR-RAM bank, CHR-RAM bank switchable via register $4518 from 256 KiB total
  • PPU $2400-$27FF: 1 KiB CIRAM or CHR-RAM bank, CHR-RAM bank switchable via register $4519 from 256 KiB total
  • PPU $2800-$2BFF: 1 KiB CIRAM or CHR-RAM bank, CHR-RAM bank switchable via register $451A from 256 KiB total
  • PPU $2C00-$2FFF: 1 KiB CIRAM or CHR-RAM bank, CHR-RAM bank switchable via register $451B from 256 KiB total

Registers

PRG-"ROM" Write-protection/Mirroring ($42FC-$42FF, write)

A~FEDC BA98 7654 3210  D~7654 3210
  -------------------    ---------
  0100 0010 1111 11PM    ...M ....
                   |+-------+------ Set nametable mirroring type
                   |                (if CIRAM is enabled)
                   |                 0: One-screen, page 0
                   |                 1: One-screen, page 1
                   |                 2: Vertical
                   |                 3: Horizontal
                   +--------------- PRG-"ROM" write-protection
                                     0: disabled, PRG-"ROM" write-enabled
                                     1: enabled, PRG-"ROM" write-protected

Configuration Register ($4500, write)

D~7654 3210
  ---------
  PMWW IcNC
  |||| |||+- CHR-RAM mode
  |||| |||    0: Game-Doctor-compatible mode, do not use $4510-$4517
  |||| |||    1: Super Magicard mode, use $4510-$4517
  |||| ||+-- Nametable mode
  |||| ||     0: CHR-RAM, use $4518-$451C
  |||| ||     1: CIRAM, mirrored according to $42FC-$42FF
  |||| |+--- Must be identical to C
  |||| +---- IRQ source select
  ||||        0: M2 rise
  ||||        1: PA12 rise (unfiltered, e.g. 8 rises per scanline)
  ||++------ Select 8 KiB WRAM bank at CPU $6000-$7FFF
  |+-------- Select memory map
  |           0: GUI/Load: $6000-$BFFF: PRG-"ROM"/WRAM
  |                        $C000-$FFFF: BIOS
  |           1: Game: $6000-$7FFF: WRAM
  |                    $8000-$FFFF: PRG-"ROM"
  +--------- Pass-through mode
              0: Disabled, show GUI or play game from PRG-"ROM"
              1: Enabled, play cartrige inserted into SMC's cartridge connector

IRQ Disable ($4501, write)

Acknowledges IRQ and disables counting.

IRQ Counter Low Byte ($4502, write)

This is the low byte of a 15-bit (D0-D14) counter that, if nonzero, is increased on every M2/PA12 rise and raises an IRQ when the counter flips from $7FFF to $0000. Writing to this register also acknowledges the IRQ.

IRQ Counter High Byte ($4503, write)

This is the high byte of a 15-bit (D0-D14) counter that, if nonzero, is increased on every M2/PA12 rise and raises an IRQ when the counter flips from $7FFF to $0000. Writing to this register also acknowledges the IRQ and enables counting.

PRG-"ROM" Bank registers ($4504-$4507, write)

  • $4504: Set 8 KiB PRG-"ROM" bank at CPU $8000-$9FFF
  • $4505: Set 8 KiB PRG-"ROM" bank at CPU $A000-$BFFF
  • $4506: Set 8 KiB PRG-"ROM" bank at CPU $C000-$DFFF
  • $4507: Set 8 KiB PRG-"ROM" bank at CPU $E000-$FFFF. Hard reset default: last bank.

CHR-RAM Bank registers ($4510-$451B, write)

  • $4510: Set 1 KiB CHR-RAM bank at PPU $0000-$03FF
  • $4511: Set 1 KiB CHR-RAM bank at PPU $0400-$07FF
  • $4512: Set 1 KiB CHR-RAM bank at PPU $0800-$0BFF
  • $4513: Set 1 KiB CHR-RAM bank at PPU $0C00-$0FFF
  • $4514: Set 1 KiB CHR-RAM bank at PPU $1000-$13FF
  • $4515: Set 1 KiB CHR-RAM bank at PPU $1400-$17FF
  • $4516: Set 1 KiB CHR-RAM bank at PPU $1800-$1BFF
  • $4517: Set 1 KiB CHR-RAM bank at PPU $1C00-$1FFF
  • $4518: Set 1 KiB CHR-RAM bank at PPU $2000-$23FF if $4500.1=0
  • $4519: Set 1 KiB CHR-RAM bank at PPU $2400-$27FF if $4500.1=0
  • $451A: Set 1 KiB CHR-RAM bank at PPU $2800-$2BFF if $4500.1=0
  • $451B: Set 1 KiB CHR-RAM bank at PPU $2C00-$2FFF if $4500.1=0

Notes

  • 512-byte Trainers are loaded and initialized by JMP/JSRing to an address specified by the header of the SMC's native file format. iNES format files lack this information. Heuristically, battery-backup games load and JMP to $5D00, non-battery games with CHR-ROM load and JMP to $7000, while CHR-ROM-less games load to $7000 and JSR to $7003 before JMPing to ($FFFC).
  • BIOS changes every game's NMI vector to a routine at $5032 that checks whether the unit's real-time save button has been pressed before passing control to the game's original NMI handler. As a result, M2-based IRQs set up in that handler will occur 75 M2 cycles later than normally.
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