NES 2.0 Mapper 432: Difference between revisions
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{{DEFAULTSORT:432}}[[Category:Multicart mappers]][[Category:MMC3-like mappers]][[Category:Mappers with scanline IRQs]] | {{DEFAULTSORT:432}}[[Category:Multicart mappers]][[Category:MMC3-like mappers]][[Category:Mappers with scanline IRQs]] | ||
'''NES 2.0 Mapper | '''NES 2.0 Mapper 432''' denotes the MMC3-based Realtec '''8090''' multicart circuit board. | ||
* ''3-in-1 High Standerd [sic] (DP-33)'' | * ''3-in-1 High Standerd [sic] (DP-33)'' | ||
* ''160000000-in-1'' (unknown cartridge code) | * ''160000000-in-1'' (unknown cartridge code) | ||
| Line 18: | Line 18: | ||
D~7654 3210 | D~7654 3210 | ||
--------- | --------- | ||
? | ?NQP CmMb | ||
| | |||+- PRG/CHR A17 if M=1 | ||| |||+- PRG/CHR A17 if M=1 | ||
| | ||+-- PRG A17 mode | ||| ||+-- PRG A17 mode | ||
| | || 0: from MMC3 (256 KiB inner bank) | ||| || 0: from MMC3 (256 KiB inner bank) | ||
| | || 1: from b (128 KiB inner bank) | ||| || 1: from b (128 KiB inner bank) | ||
| | |+--- CHR A17 mode | ||| |+--- CHR A17 mode | ||
| | | 0: from MMC3 (256 KiB inner bank) | ||| | 0: from MMC3 (256 KiB inner bank) | ||
| | | 1: from b (128 KiB inner bank) | ||| | 1: from b (128 KiB inner bank) | ||
| | +---- CHR A18 | ||| +---- CHR A18 | ||
| +------ PRG A18 | ||+------ PRG A18 | ||
|+------- PRG+CHR A19 | |||
+-------- NROM-128 mode (1=enabled) | +-------- NROM-128 mode (1=enabled) | ||
Latest revision as of 13:06, 2 June 2024
NES 2.0 Mapper 432 denotes the MMC3-based Realtec 8090 multicart circuit board.
- 3-in-1 High Standerd [sic] (DP-33)
- 160000000-in-1 (unknown cartridge code)
Solder Pad Enable Register ($6000-$7FFE, even)
Mask: $E001
D~7654 3210
---------
.... ...S
+- 1=Replace PRG-ROM with solder pad value
in the CPU $8000-$FFFF address range
Outer Bank Register ($6001-$7FFF, odd)
Mask: $E001 D~7654 3210 --------- ?NQP CmMb ||| |||+- PRG/CHR A17 if M=1 ||| ||+-- PRG A17 mode ||| || 0: from MMC3 (256 KiB inner bank) ||| || 1: from b (128 KiB inner bank) ||| |+--- CHR A17 mode ||| | 0: from MMC3 (256 KiB inner bank) ||| | 1: from b (128 KiB inner bank) ||| +---- CHR A18 ||+------ PRG A18 |+------- PRG+CHR A19 +-------- NROM-128 mode (1=enabled)
As it uses the MMC3 clones's WRAM interface, writing to the outer bank register requires enabling and not write-protecting WRAM in the MMC's $A001 register. NROM-128 mode forces the MMC3 clone's CPU A14 input low, causing MMC3 register 6 to select both the bank at $8000 and $C000, and register 7 to select both the bank at $A000 and $E000.
MMC3-compatible registers ($8000-$FFFF)
Mask: $E001
See MMC3.
