CPU Test Mode: Difference between revisions

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== 2A03E / 2A03G Test Mode ==
Pin 30 on the 2A03G and 2A03H provides special functionality in some revisions of the chip and is normally grounded.
Pin 30 of the 2A03 revision G can be activated to enable a special test mode for the APU. This activates registers for testing the APU at $4018-$401A at the expense of deactivating the joypad input registers at $4016-$4017:
 
== 2A03G / 2A03H Test Mode ==
Pin 30 of the 2A03G and 2A03H can be asserted to enable a special test mode for the APU. This activates registers for testing the APU at $4018-$401A at the expense of deactivating the joypad input registers at $4016-$4017:  
  R$4018: [BBBB AAAA] - current instant DAC value of B=pulse2 and A=pulse1 (either 0 or current volume)
  R$4018: [BBBB AAAA] - current instant DAC value of B=pulse2 and A=pulse1 (either 0 or current volume)
  R$4019: [NNNN TTTT] - current instant DAC value of N=noise (either 0 or current volume) and T=triangle (anywhere from 0 to 15)
  R$4019: [NNNN TTTT] - current instant DAC value of N=noise (either 0 or current volume)  
  R$401A: [.DDD DDDD] - current instant DAC value of DPCM channel
                      and T=triangle (anywhere from 0 to 15)
  W$401A: [L..T TTTT] - "lock channel output" and set current instant phase of triangle
  R$401A: [.DDD DDDD] - current instant DAC value of DPCM channel (same as value written to $4011)
                      (What is the polarity of L? How does it work?)
  W$401A: [L..T TTTT] - set state of triangle's sequencer to T, and lock all channels if L=1
                      (pulse+noise always output current volume, triangle/DPCM no longer advance)
 
Test mode disconnects the external CPU bus from the internal bus when reading from any of $4000-401F, just as normally happens when reading from $4015; this is what disables the joypads, by preventing the CPU from seeing the value they put on the bus. Test mode also causes the CPU to continue outputting M2 while held in reset.
 
Connecting pin 30 to CPU A3 allows the test and controller registers to coexist, at the cost of increased likelihood of DMC DMA corruption when the CPU is reading from $4000-401F (see [[DMA#Register_conflicts|DMA register conflicts]]). Because the state of A3 is effectively random when reset begins and because the address lines go high impedance during reset, a weak pulldown (10k Ohm) should be used to prevent pin 30 from floating while reset is held and restore standard M2-during-reset behavior.
 
== 2A03E ==
On the 2A03E, pin 30 functions as an external /RDY input, and the [//nesdev.org/Playchoice.pdf Playchoice 10] supervisor CPU uses this to reset the 2A03E when the player runs out of time (by driving pin 30 high to halt it, then driving pin 30 low and pulling /RESET low to reset it). Driving pin 30 high and then low has been observed to simply crash the 2A03E.


The schematic for the [//nesdev.org/Playchoice.pdf Playchoice 10] implies that this functionality is also in the 2A03E. There it is used by the supervisor CPU to lock out controller input until coins are given to the arcade machine.
== 2A07A ==
Just as with the 2A03E, pin 30 on the 2A07 is an external /RDY input.


== 2A03letterless Programmable Interval Timer ==
== 2A03 ==
Visual inspection of the original 2A03 revision indicates there was planned IRQ functionality from $401C-$401F, but this was left unfinished and unusable and was outright removed from later CPU revisions.
In the original version of the 2A03, pin 30 is not connected to anything at all.
W$401C,D,E: write lower, middle, upper bits of counter reload value
R$401C,D,E: read lower, middle, upper bits of current counter value
W$401F: [ELAC DTZC]
          |||| ||||
          |||+----+-- Clock source
          |||  |||    00: M2÷16  10: M2÷256
          |||  |||    01: Rising edges of JOY2  11: Falling edges of JOY2
          |||  ||+--- Exists but does nothing. Toggles (invisibly) on terminal count.
          |||  |+---- Value driven out on JOY1. Toggles on terminal count.
          |||  +----- 1:count up; 0:count down
          ||+-------- 1:automatic reload when counter reaches 0; 0:counter stops while zero
          |+--------- 1:reload immediately
          +---------- 1:IRQ enabled (counts regardless)
R$401F: [E... ...I]
          |      |
          |      +-- Timer IRQ would be asserted if enabled
          +---------- IRQ is enabled
        Reads from $401F acknowledge the IRQ


== See also ==
== See also ==
* Forum: [http://forums.nesdev.org/viewtopic.php?f=9&t=9197 Breaking NES apart (WARNING: traffic)]
* Forum: [http://forums.nesdev.org/viewtopic.php?f=9&t=9197 Breaking NES apart]
* Forum: [http://forums.nesdev.org/viewtopic.php?f=9&t=14421 Memory map and 2A03 register map / 2A03 cutting-room floormetal]
* See: [[:File:Apu address.jpg]]
* See: [[:File:Apu address.jpg]]
* See: [[CPU pin out and signal description]]
* See: [[CPU pin out and signal description]]

Latest revision as of 14:23, 28 May 2024

Pin 30 on the 2A03G and 2A03H provides special functionality in some revisions of the chip and is normally grounded.

2A03G / 2A03H Test Mode

Pin 30 of the 2A03G and 2A03H can be asserted to enable a special test mode for the APU. This activates registers for testing the APU at $4018-$401A at the expense of deactivating the joypad input registers at $4016-$4017: 

R$4018: [BBBB AAAA] - current instant DAC value of B=pulse2 and A=pulse1 (either 0 or current volume)
R$4019: [NNNN TTTT] - current instant DAC value of N=noise (either 0 or current volume) 
                      and T=triangle (anywhere from 0 to 15)
R$401A: [.DDD DDDD] - current instant DAC value of DPCM channel (same as value written to $4011)
W$401A: [L..T TTTT] - set state of triangle's sequencer to T, and lock all channels if L=1
                      (pulse+noise always output current volume, triangle/DPCM no longer advance)

Test mode disconnects the external CPU bus from the internal bus when reading from any of $4000-401F, just as normally happens when reading from $4015; this is what disables the joypads, by preventing the CPU from seeing the value they put on the bus. Test mode also causes the CPU to continue outputting M2 while held in reset.

Connecting pin 30 to CPU A3 allows the test and controller registers to coexist, at the cost of increased likelihood of DMC DMA corruption when the CPU is reading from $4000-401F (see DMA register conflicts). Because the state of A3 is effectively random when reset begins and because the address lines go high impedance during reset, a weak pulldown (10k Ohm) should be used to prevent pin 30 from floating while reset is held and restore standard M2-during-reset behavior.

2A03E

On the 2A03E, pin 30 functions as an external /RDY input, and the Playchoice 10 supervisor CPU uses this to reset the 2A03E when the player runs out of time (by driving pin 30 high to halt it, then driving pin 30 low and pulling /RESET low to reset it). Driving pin 30 high and then low has been observed to simply crash the 2A03E.

2A07A

Just as with the 2A03E, pin 30 on the 2A07 is an external /RDY input.

2A03

In the original version of the 2A03, pin 30 is not connected to anything at all.

See also

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