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The '''2A03''', short for RP2A03[G], is the common name of the NTSC [[CPU|NES CPU]] chip. It consists of a MOS Technology 6502 processor (lacking decimal mode) and audio generation logic.
The [[2A03]], short for RP2A03, is the common name of the NTSC [[CPU|NES CPU]] chip. It consists of a MOS Technology 6502 processor (lacking decimal mode) and audio, joypad, and DMA functionality. PAL systems use the similar RP2A07, which has a different clock rate, adjusted sampled audio rates, and DMA bugfixes.
The 2A03 is used only in NTSC consoles; PAL systems are equipped with an RP2A07G chip, whose only major changes are a different clock divider (divide by 16 instead of 12) and adjusted PCM playback speeds.


== 2A03 register map ==
== 2A03 register map ==
In addition to the registers in the 6502 core, the 2A03 contains 22 memory-mapped registers for sound generation (see [[APU|NES APU]]), joystick reading, and OAM DMA transferring. Unlike the addresses of [[PPU]] registers and [[MMC|mapper]] registers, CPU register addresses are completely decoded, which means that the entire space from the end of CPU registers to the top of address space (<tt>$4020</tt> through <tt>$FFFF</tt>) is available to the Game Pak.
In addition to the registers in the 6502 core, the 2A03 contains 22 memory-mapped registers for sound generation (see [[APU|NES APU]]), joystick reading, and OAM DMA transferring. Unlike the addresses of [[PPU]] registers and [[MMC|mapper]] registers, CPU register addresses are completely decoded, which means that the entire space from the end of CPU registers to the top of address space ($4020 through $FFFF) is available to the Game Pak.


The range <tt>$4018</tt>–<tt>$401F</tt> does nothing on a retail NES. It was intended for 2A03 functionality that never made it to production. Various revisions of the 2A03 include [[CPU Test Mode|test registers]] (which are disabled in normal operation) or [http://forums.nesdev.org/viewtopic.php?f=9&t=14421 remnants of an incompletely implemented IRQ counter] that was disconnected from the rest of the circuit.
The range $4018-$401F does nothing on a retail NES. It was intended for 2A03 functionality that never made it to production. Various revisions of the 2A03 include [[CPU Test Mode|test registers]] (which are disabled in normal operation) or [[RP2A03 Programmable Interval Timer|remnants of an incompletely implemented IRQ counter]] that was disconnected from the rest of the circuit. Mappers can place writable registers here without conflicting with the 2A03, but placing readable registers here should be avoided because of [[DMA#Register_conflicts|conflicts with DMA]].


{| class="wikitable"
{| class="wikitable"
|<tt>$4000</tt> || SQ1_VOL || Duty and volume for [[APU Pulse|square wave 1]]
!Address || Name || colspan=2 | Write || Read
|-
|-
|<tt>$4001</tt> || SQ1_SWEEP || Sweep control register for square wave 1
|$4000 || SQ1_VOL || rowspan=4 | [[APU Pulse|Pulse 1]] || Duty cycle and [[APU Envelope|volume]] || rowspan=21 | [[Open bus]]
|-
|-
|<tt>$4002</tt> || SQ1_LO || Low byte of period for square wave 1
|$4001 || SQ1_SWEEP || [[APU Sweep|Sweep control register]]
|-
|-
|<tt>$4003</tt> || SQ1_HI || High byte of period and length counter value for square wave 1
|$4002 || SQ1_LO || Low byte of period
|-
|-
|<tt>$4004</tt> || SQ2_VOL || Duty and volume for [[APU Pulse|square wave 2]]
|$4003 || SQ1_HI || High byte of period and [[APU Length Counter|length counter value]]
|-
|-
|<tt>$4005</tt> || SQ2_SWEEP || Sweep control register for square wave 2
|$4004 || SQ2_VOL || rowspan=4 | [[APU Pulse|Pulse 2]] || Duty cycle and [[APU Envelope|volume]]
|-
|-
|<tt>$4006</tt> || SQ2_LO || Low byte of period for square wave 2
|$4005 || SQ2_SWEEP || [[APU Sweep|Sweep control register]]
|-
|-
|<tt>$4007</tt> || SQ2_HI || High byte of period and length counter value for square wave 2
|$4006 || SQ2_LO || Low byte of period
|-
|-
|<tt>$4008</tt> || TRI_LINEAR || [[APU Triangle|Triangle wave]] linear counter
|$4007 || SQ2_HI || High byte of period and [[APU Length Counter|length counter value]]
|-
|-
|<tt>$4009</tt> || || Unused, but is eventually accessed in memory-clearing loops
|$4008 || TRI_LINEAR || rowspan=4 | [[APU Triangle|Triangle]] || Linear counter
|-
|-
|<tt>$400A</tt> || TRI_LO || Low byte of period for triangle wave
|$4009 || || Unused
|-
|-
|<tt>$400B</tt> || TRI_HI || High byte of period and length counter value for triangle wave
|$400A || TRI_LO || Low byte of period
|-
|-
|<tt>$400C</tt> || NOISE_VOL || Volume for [[APU Noise|noise generator]]
|$400B || TRI_HI || High byte of period and [[APU Length Counter|length counter value]]
|-
|-
|<tt>$400D</tt> || || Unused, but is eventually accessed in memory-clearing loops
|$400C || NOISE_VOL || rowspan=4 | [[APU Noise|Noise]] || [[APU Envelope|Volume]]
|-
|-
|<tt>$400E</tt> || NOISE_LO || Period and waveform shape for noise generator
|$400D || || Unused
|-
|-
|<tt>$400F</tt> || NOISE_HI || Length counter value for noise generator
|$400E || NOISE_LO || Period and waveform shape
|-
|-
|<tt>$4010</tt> || DMC_FREQ || Play mode and frequency for [[APU DMC|DMC samples]]
|$400F || NOISE_HI || [[APU Length Counter|Length counter value]]
|-
|-
|<tt>$4011</tt> || DMC_RAW || 7-bit DAC
|$4010 || DMC_FREQ || rowspan=4 | [[APU DMC|DMC]] || IRQ flag, loop flag and frequency
|-
|-
|<tt>$4012</tt> || DMC_START || Start of DMC waveform is at address <tt>$C000</tt> + <tt>$40</tt> × <tt>$xx</tt>
|$4011 || DMC_RAW || 7-bit DAC
|-
|-
|<tt>$4013</tt> || DMC_LEN || Length of DMC waveform is <tt>$10</tt> × <tt>$xx</tt> + 1 bytes (128 × <tt>$xx</tt> + 8 samples)
|$4012 || DMC_START || Start address = $C000 + $40*$xx
|-
|-
|<tt>$4014</tt> || [[OAMDMA]] || Writing <tt>$xx</tt> copies 256 bytes by reading from <tt>$xx00</tt>–<tt>$xxFF</tt> and writing to [[OAMDATA]] (<tt>$2004</tt>)
|$4013 || DMC_LEN || Sample length = $10*$xx + 1 bytes (128*$xx + 8 samples)
|-
|-
|<tt>$4015</tt> || SND_CHN || [[APU Status|Sound channels enable and status]]
|$4014 || OAMDMA || colspan=2 | [[OAMDMA|OAM DMA]]: Copy 256 bytes from $xx00-$xxFF into OAM via [[OAMDATA]] ($2004)
|-
|-
|<tt>$4016</tt> || JOY1 || [[Input_devices|Joystick 1 data (R) and joystick strobe (W)]]
|$4015 || SND_CHN || colspan=2 | [[APU Status|Sound channels enable]] || [[APU Status|Sound channel and IRQ status]]
|-
|-
|<tt>$4017</tt> || JOY2 || Joystick 2 data (R) and [[APU Frame Counter|frame counter]] control (W)
|$4016 || JOY1 || colspan=2 | [[Input devices|Joystick strobe]] || [[Input devices|Joystick 1 data]]
|-
|-
|colspan="2" | <tt>$4018</tt>–<tt>$401F</tt> || APU and I/O functionality that is normally disabled. See [[CPU Test Mode]].
|$4017 || JOY2 || colspan=2 | [[APU Frame Counter|Frame counter]] control || [[Input devices|Joystick 2 data]]
|-
|colspan="2" | $4018-$401A || colspan=3 | APU test functionality that is normally disabled. See [[CPU Test Mode]].
|-
|colspan="2" | $401C-$401F || colspan=3 | Unfinished IRQ timer functionality that is always disabled. See [[RP2A03 Programmable Interval Timer]].
|}
|}


==See also==
==See also==
*[[CPU|NES CPU]]
*[[CPU|NES CPU]]

Latest revision as of 20:34, 8 October 2023

The 2A03, short for RP2A03, is the common name of the NTSC NES CPU chip. It consists of a MOS Technology 6502 processor (lacking decimal mode) and audio, joypad, and DMA functionality. PAL systems use the similar RP2A07, which has a different clock rate, adjusted sampled audio rates, and DMA bugfixes.

2A03 register map

In addition to the registers in the 6502 core, the 2A03 contains 22 memory-mapped registers for sound generation (see NES APU), joystick reading, and OAM DMA transferring. Unlike the addresses of PPU registers and mapper registers, CPU register addresses are completely decoded, which means that the entire space from the end of CPU registers to the top of address space ($4020 through $FFFF) is available to the Game Pak.

The range $4018-$401F does nothing on a retail NES. It was intended for 2A03 functionality that never made it to production. Various revisions of the 2A03 include test registers (which are disabled in normal operation) or remnants of an incompletely implemented IRQ counter that was disconnected from the rest of the circuit. Mappers can place writable registers here without conflicting with the 2A03, but placing readable registers here should be avoided because of conflicts with DMA.

Address Name Write Read
$4000 SQ1_VOL Pulse 1 Duty cycle and volume Open bus
$4001 SQ1_SWEEP Sweep control register
$4002 SQ1_LO Low byte of period
$4003 SQ1_HI High byte of period and length counter value
$4004 SQ2_VOL Pulse 2 Duty cycle and volume
$4005 SQ2_SWEEP Sweep control register
$4006 SQ2_LO Low byte of period
$4007 SQ2_HI High byte of period and length counter value
$4008 TRI_LINEAR Triangle Linear counter
$4009 Unused
$400A TRI_LO Low byte of period
$400B TRI_HI High byte of period and length counter value
$400C NOISE_VOL Noise Volume
$400D Unused
$400E NOISE_LO Period and waveform shape
$400F NOISE_HI Length counter value
$4010 DMC_FREQ DMC IRQ flag, loop flag and frequency
$4011 DMC_RAW 7-bit DAC
$4012 DMC_START Start address = $C000 + $40*$xx
$4013 DMC_LEN Sample length = $10*$xx + 1 bytes (128*$xx + 8 samples)
$4014 OAMDMA OAM DMA: Copy 256 bytes from $xx00-$xxFF into OAM via OAMDATA ($2004)
$4015 SND_CHN Sound channels enable Sound channel and IRQ status
$4016 JOY1 Joystick strobe Joystick 1 data
$4017 JOY2 Frame counter control Joystick 2 data
$4018-$401A APU test functionality that is normally disabled. See CPU Test Mode.
$401C-$401F Unfinished IRQ timer functionality that is always disabled. See RP2A03 Programmable Interval Timer.

See also

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