INES Mapper 095: Difference between revisions

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(add some m095 analysis, confirmation of Lidnariq's guesses)
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[[Category:iNES Mappers]][[Category:MMC3-like mappers]]
[[Category:iNES Mappers|095]][[Category:MMC3-like mappers|095]][[Category:in NesCartDB|095]]
What's written below is suspect, because the Namco 108 mapper does not have C or P bits, and sacrificing 32kB of CHR ROM just for the ability to swap between 1ScA/1ScB/horizontal mirroring seems like a weird tradeoff.  
Mapper 95 represents '''NAMCOT-3425''', a board used only for the game [https://nescartdb.com/profile/view/1806/dragon-buster Dragon Buster (J)].


---
It is to the ordinary Namco 108 family boards ([[iNES Mapper 206|mapper 206]]) as TKSROM and TLSROM ([[iNES Mapper 118|mapper 118]]) is to ordinary [[MMC3]] boards.
Instead of having hardwired mirroring like mapper 206, it has CHR A15 directly controlling CIRAM A10, just as CHR A17 controls CIRAM A10 on TxSROM.
Only horizontal mirroring and 1-screen mirroring are possible because the Namco 108 lacks the C bit of MMC3.


Dragon Buster (J) needs nametable rewiring to be emulated (based on bit 5 of the CHR regs) in order to work. The special description here for C and P bits is redundant, although reasonable from a certain less than completely synthesized point of view, as the result of MMC3's C mode bit is to yield CHR R0 and R1 as described in disch's doc when cleared and R2-5 when set. Therefore, this board must be a normal MMC3 but rewiring bit 5 of CHR to the nametable control.  
''Dragon Buster'' has only 32 KiB of CHR ROM, but homebrew using this mapper could use the full 64 KiB through careful arrangement of CHR ROM to put game background tiles in one half (which would always use one nametable) and status bar and menu tiles in the other half (which would always use the other nametable).


Here's another way of looking at it. This game only has 32K of CHR, so they repurposed the next CHR mapping bit to be nametable control. Why not?
Disch's older notes described an extended and mistaken version of this mapper with a full MMC3, so some emulators may be doing it that way. That extended version is identical to mapper 118, except CHR A15 (bank bit 5) controls CIRAM A10 instead of CHR A17 (bank bit 7).


We should be able to rewrite this documentation to mention only the CHR->nametable bit wiring.
Here's a terse pseudocode:
chr_rom_addr = namco108_chrmap(ppu_addr&0x1FFF) & 0xFFFF;
ciram_addr = ((namco108_chrmap(ppu_addr&0x1FFF)>>15)<<10) | (ppu_addr&0x03FF);


  Here are Disch's original notes:
=== Bank select ($8000-$9FFE, even) ===
  ========================
  7  bit  0
  = Mapper 095          =
---- ----
  ========================
  xxxx xRRR
 
      |||
  aka
      +++- Specify which bank register to update on next write to Bank Data register
  --------------------------
            0: Select 2 KB CHR bank at PPU $0000-$07FF and nametable at PPU $2000-$27FF
  MMC3 (modified)
            1: Select 2 KB CHR bank at PPU $0800-$0FFF and nametable at PPU $2800-$2FFF
 
            2: Select 1 KB CHR bank at PPU $1000-$13FF
 
            3: Select 1 KB CHR bank at PPU $1400-$17FF
  Example Game:
            4: Select 1 KB CHR bank at PPU $1800-$1BFF
  --------------------------
            5: Select 1 KB CHR bank at PPU $1C00-$1FFF
  Dragon Buster (J)
            6: Select 8 KB PRG ROM bank at $8000-$9FFF
 
            7: Select 8 KB PRG ROM bank at $A000-$BFFF
 
 
  Notes:
=== Bank data ($8001-$9FFF, odd) ===
  ---------------------------
7  bit  0
  This mapper is a modified [[MMC3]].  It behaves exactly like your normal MMC3, only mirroring is handled
---- ----
  differently.  For details on MMC3, refer to [[INES Mapper 004|mapper 004]].
..ND DDDD
 
  || ||||
 
  |+-++++- New bank value, based on last value written to Bank select register
  Regs:
  |          All registers as standard [[iNES Mapper 206|Namco 108]]
  ---------------------------
  |
 
  +------- Nametable select, based on last value written to Bank select register
  $8000:  [CP.. .AAA]
              0: Select Nametable A
    C = CHR Mode
              1: Select Nametable B
    P = PRG Mode
    A = Address for $8001
 
 
  This register operates exactly like it does on your normal MMC3.  It is mentioned here because the 'C' bit
  has another usage for mirroring.
 
 
 
  The normal mirroring reg ($A000) is totally ignored, and the CHR regs select nametables:
 
  When 'C' is set:
    [ R:2 ][ R:3 ]
    [ R:4 ][ R:5 ]
 
  When 'C' is clear:
    [ R:0 ][ R:0 ]
    [ R:1 ][ R:1 ]
 
 
  For mirroring, only bit 5 of the CHR regs is significant.  Bit 5 of the appropriate reg selects either NTA or
  NTB.

Latest revision as of 01:35, 14 September 2023

Mapper 95 represents NAMCOT-3425, a board used only for the game Dragon Buster (J).

It is to the ordinary Namco 108 family boards (mapper 206) as TKSROM and TLSROM (mapper 118) is to ordinary MMC3 boards. Instead of having hardwired mirroring like mapper 206, it has CHR A15 directly controlling CIRAM A10, just as CHR A17 controls CIRAM A10 on TxSROM. Only horizontal mirroring and 1-screen mirroring are possible because the Namco 108 lacks the C bit of MMC3.

Dragon Buster has only 32 KiB of CHR ROM, but homebrew using this mapper could use the full 64 KiB through careful arrangement of CHR ROM to put game background tiles in one half (which would always use one nametable) and status bar and menu tiles in the other half (which would always use the other nametable).

Disch's older notes described an extended and mistaken version of this mapper with a full MMC3, so some emulators may be doing it that way. That extended version is identical to mapper 118, except CHR A15 (bank bit 5) controls CIRAM A10 instead of CHR A17 (bank bit 7).

Here's a terse pseudocode: 

chr_rom_addr = namco108_chrmap(ppu_addr&0x1FFF) & 0xFFFF;
ciram_addr = ((namco108_chrmap(ppu_addr&0x1FFF)>>15)<<10) | (ppu_addr&0x03FF);

Bank select ($8000-$9FFE, even)

7  bit  0
---- ----
xxxx xRRR
      |||
      +++- Specify which bank register to update on next write to Bank Data register
           0: Select 2 KB CHR bank at PPU $0000-$07FF and nametable at PPU $2000-$27FF
           1: Select 2 KB CHR bank at PPU $0800-$0FFF and nametable at PPU $2800-$2FFF
           2: Select 1 KB CHR bank at PPU $1000-$13FF
           3: Select 1 KB CHR bank at PPU $1400-$17FF
           4: Select 1 KB CHR bank at PPU $1800-$1BFF
           5: Select 1 KB CHR bank at PPU $1C00-$1FFF
           6: Select 8 KB PRG ROM bank at $8000-$9FFF
           7: Select 8 KB PRG ROM bank at $A000-$BFFF

Bank data ($8001-$9FFF, odd)

7  bit  0
---- ----
..ND DDDD
  || ||||
  |+-++++- New bank value, based on last value written to Bank select register
  |          All registers as standard Namco 108
  |
  +------- Nametable select, based on last value written to Bank select register
             0: Select Nametable A
             1: Select Nametable B
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