|
|
| (One intermediate revision by the same user not shown) |
| Line 1: |
Line 1: |
| {{DEFAULTSORT:126}}[[Category:Multicart mappers|126]][[Category:Mappers with CHR RAM|126]][[Category:Mappers with scanline IRQs|126]][[Category:MMC3-like mappers|126]]
| | #REDIRECT [[NES 2.0 Mapper 534]] |
| '''iNES Mapper 126''' denotes an MMC3-based multicart mapper with an optional (C)NROM-like PRG and CHR banking modes.
| |
| * ''Power Joy Classic TV Game 84-in-1 (PJ-008)''
| |
| * ''Gamezone 118-in-1 (AT-207)''
| |
| | |
| ==MMC3-compatible registers ($8000-$FFFF, write)==
| |
| These registers function identically to a normal [[MMC3]].
| |
| | |
| ==Outer Bank/PRG Mask Register ($6000, write)==
| |
| Mask: $E003
| |
|
| |
| D~7654 3210
| |
| ---------
| |
| XYBB CPPp
| |
| |||| |||+- PRG A17 if Y=1
| |
| ||++-|+++- PRG A21..A18
| |
| |||| +---- CHR A17 if X=1
| |
| |||+------ CHR A19
| |
| ||+------- CHR A18
| |
| |+-------- PRG A17 mode
| |
| | 0: PRG A17=MMC3 PRG A17 (256 KiB inner PRG bank size)
| |
| | 1: PRG A17=p (128 KiB inner PRG bank)
| |
| +--------- CHR A17 mode
| |
| 0: CHR A17=MMC3 CHR A17 (256 KiB inner CHR bank size)
| |
| 1: CHR A17=C (128 KiB inner CHR bank)
| |
| | |
| Note the reverse-ordered CHR A18/A19 bits.
| |
| ==Miscellaneous Register ($6001, write)==
| |
| Mask: $E003
| |
|
| |
| D~7654 3210
| |
| ---------
| |
| .... ..?M
| |
| +- 0: CPU $8000-$FFFF reads PRG-ROM
| |
| 1: CPU $8000-$FFFF reads solder pad (D0/D1)
| |
| | |
| ==Inner CHR Bank Register ($6002, write)==
| |
| Mask: $E003
| |
|
| |
| D~7654 3210
| |
| ---------
| |
| ...M CCCC
| |
| | ++++- CHR A16..A13 in CNROM mode,
| |
| | ignored otherwise
| |
| +------ 1=CNROM-128 mode, 0=CNROM-256 mode
| |
| | |
| The CNROM bit matters when the Lock bit is set: In CNROM-256 mode, bits 0 and 1 are still writable, in CNROM-128 mode, only bit 0 is writable.
| |
| ==Mode Register ($6003, write)==
| |
| Mask: $E003
| |
|
| |
| D~7654 3210
| |
| ---------
| |
| L..C .?PP
| |
| | | ++- PRG Banking Mode
| |
| | | 0: MMC3
| |
| | | 1: NROM-128: PRG A14=MMC3 PRG A14
| |
| | | 2: NROM-128: Same as 1
| |
| | | 3: NROM-256: PRG A14=CPU A14
| |
| | +------ CHR Banking Mode
| |
| | 0: MMC3
| |
| | 1: CNROM
| |
| +--------- Lock registers $6000-$6003 except $6002.0/1
| |
| | |
| NROM PRG banking mode is implemented by holding the MMC3 clones' CPU A13 and A14 input low. This means that...
| |
| * MMC3 register #6 applies across the entire CPU $8000-$FFFF address range;
| |
| * the MMC3's PRG A13 output is substituted with CPU A13;
| |
| * in NROM-256 mode, the MMC3's PRG A14 output substituted with CPU A14;
| |
| * MMC3 $8000.6 bits 1-3 therefore select a 16 KiB inner bank number.
| |
| | |
| CNROM CHR banking mode is implemented by using register $6002 as a source for an 8 KiB inner bank number instead of the MMC3's CHR registers.
| |
| | |
| ==Note==
| |
| * Outer bank registers overlay any WRAM, and can only be written to if WRAM is enabled in the MMC3 ($A001=$80).
| |
| * Register $6002 bit 0, and 1 in CNROM-256 mode, are not affected by the Lock bit in register $6003.
| |
| * [[NES 2.0 Mapper 534]] is almost identical. It connects the higher CHR address lines differently, and MMC3 register $C000 takes the inverted value.
| |
| * The common dump of ''Gamezone 118-in-1 (AT-207)'' inverts CHR A18, which may be a protection feature or an incorrect dump.
| |
