CPU memory map: Difference between revisions
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! Address range || Size || Device | ! Address range || Size || Device | ||
|- | |- | ||
| $ | | $0000–$07FF || $0800 || 2 KB internal RAM | ||
|- | |- | ||
| $ | | $0800–$0FFF || $0800 ||rowspan=3| [[Mirroring#Memory Mirroring|Mirrors]] of $0000–$07FF | ||
|- | |- | ||
| $ | | $1000–$17FF || $0800 | ||
|- | |- | ||
| $ | | $1800–$1FFF || $0800 | ||
|- | |- | ||
| $ | | $2000–$2007 || $0008 || [[PPU registers|NES PPU registers]] | ||
|- | |- | ||
| $ | | $2008–$3FFF || $1FF8 || Mirrors of $2000–$2007 (repeats every 8 bytes) | ||
|- | |- | ||
| $ | | $4000–$4017 || $0018 || [[APU|NES APU]] and [[2A03|I/O registers]] | ||
|- | |- | ||
| $ | | $4018–$401F || $0008 || APU and I/O functionality that is normally disabled. See [[CPU Test Mode]]. | ||
|- | |- | ||
| $ | | $4020–$FFFF || $BFE0 || Cartridge space: PRG ROM, PRG RAM, and [[mapper]] registers (see note) | ||
|} | |} | ||
Some parts of the 2 KiB of internal RAM at $ | Some parts of the 2 KiB of internal RAM at $0000–$07FF have predefined purposes dictated by the 6502 architecture. | ||
The zero page is $ | The zero page is $0000–$00FF, and the stack always uses some part of the $0100–$01FF page. | ||
Games may divide up the rest however the programmer deems useful. | Games may divide up the rest however the programmer deems useful. | ||
See [[Sample RAM map]] for an example allocation strategy for this RAM. | See [[Sample RAM map]] for an example allocation strategy for this RAM. | ||
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Note: Most common boards and iNES mappers address ROM and Save/Work RAM in this format: | Note: Most common boards and iNES mappers address ROM and Save/Work RAM in this format: | ||
*$ | *$6000–$7FFF = Battery Backed Save or Work RAM | ||
*$ | *$8000–$FFFF = Usual ROM, commonly with Mapper Registers (see [[MMC1]] and [[UxROM]] for example) | ||
If using [[APU DMC|DMC audio]]: | If using [[APU DMC|DMC audio]]: | ||
*$ | *$C000–$FFF1 = DPCM samples | ||
The CPU expects interrupt vectors in a fixed place at the end of the cartridge space: | The CPU expects interrupt vectors in a fixed place at the end of the cartridge space: | ||
*$ | *$FFFA–$FFFB = NMI vector | ||
*$ | *$FFFC–$FFFD = Reset vector | ||
*$ | *$FFFE–$FFFF = IRQ/BRK vector | ||
If a mapper doesn't fix $ | If a mapper doesn't fix $FFFA–$FFFF to some known bank (typically, along with the rest of the bank containing them, e.g. $C000–$FFFF for a 16KiB banking mapper) or use some sort of reset detection, the vectors need to be stored in all banks. | ||
Revision as of 06:35, 11 January 2023
| Address range | Size | Device |
|---|---|---|
| $0000–$07FF | $0800 | 2 KB internal RAM |
| $0800–$0FFF | $0800 | Mirrors of $0000–$07FF |
| $1000–$17FF | $0800 | |
| $1800–$1FFF | $0800 | |
| $2000–$2007 | $0008 | NES PPU registers |
| $2008–$3FFF | $1FF8 | Mirrors of $2000–$2007 (repeats every 8 bytes) |
| $4000–$4017 | $0018 | NES APU and I/O registers |
| $4018–$401F | $0008 | APU and I/O functionality that is normally disabled. See CPU Test Mode. |
| $4020–$FFFF | $BFE0 | Cartridge space: PRG ROM, PRG RAM, and mapper registers (see note) |
Some parts of the 2 KiB of internal RAM at $0000–$07FF have predefined purposes dictated by the 6502 architecture. The zero page is $0000–$00FF, and the stack always uses some part of the $0100–$01FF page. Games may divide up the rest however the programmer deems useful. See Sample RAM map for an example allocation strategy for this RAM.
Note: Most common boards and iNES mappers address ROM and Save/Work RAM in this format:
- $6000–$7FFF = Battery Backed Save or Work RAM
- $8000–$FFFF = Usual ROM, commonly with Mapper Registers (see MMC1 and UxROM for example)
If using DMC audio:
- $C000–$FFF1 = DPCM samples
The CPU expects interrupt vectors in a fixed place at the end of the cartridge space:
- $FFFA–$FFFB = NMI vector
- $FFFC–$FFFD = Reset vector
- $FFFE–$FFFF = IRQ/BRK vector
If a mapper doesn't fix $FFFA–$FFFF to some known bank (typically, along with the rest of the bank containing them, e.g. $C000–$FFFF for a 16KiB banking mapper) or use some sort of reset detection, the vectors need to be stored in all banks.
