Registers: Difference between revisions

From NESdev Wiki
Jump to navigationJump to search
m (1 revision: Rest of pages not related to reference)
 
(2a03 register map)
 
(2 intermediate revisions by the same user not shown)
Line 1: Line 1:
For nesasm.
Registers provide internal state storage for a device.
<pre>
 
; -- registers.h -- ;
These may store a number, like the accumulator register in the [[CPU]],
; PPU
or they may store other behaviour states, like the colour output of the [[PPU]].
    .org 0x2000
The various cartridge [[mapper]]s have registers that control [[banking]],
PPU_CTRL1 .ds 1
as well as other devices (e.g. [[IRQ]] timer).
PPU_CTRL2 .ds 1
 
PPU_STATUS .ds 1
A register might be entirely internal, or it might have a memory mapped address
SPR_ADDR .ds 1
to provide external access via the CPU.
SPR_IO .ds 1
Such registers are often referred to by this write address.
VRAM_ADDR1 .ds 1
 
VRAM_ADDR2 .ds 1
See:
VRAM_IO .ds 1
* [[CPU registers]]
; pAPU
* [[PPU registers]]
    .org 0x4000
* [[APU registers]]
SND_PULSE1_CTRL .ds 1
* [[2A03|2A03 register map]]
SND_PULSE1_RAMP_CTRL .ds 1
SND_PULSE1_FT .ds 1
SND_PULSE1_CT .ds 1
SND_PULSE2_CTRL .ds 1
SND_PULSE2_RAMP_CTRL .ds 1
SND_PULSE2_FT .ds 1
SND_PULSE2_CT .ds 1
SND_TRI_CTRL1 .ds 1
SND_TRI_CTRL2 .ds 1
SND_TRI_FREQ1 .ds 1
SND_TRI_FREQ2 .ds 1
SND_NOISE_CTRL1 .ds 1
SND_NOISE_CTRL2 .ds 1
SND_NOISE_FREQ1 .ds 1
SND_NOISE_FREQ2 .ds 1
SND_DMC_CTRL .ds 1
SND_DMC_DA .ds 1
SND_DMC_ADDR .ds 1
SND_DMC_DL .ds 1
SPR_DMA .ds 1
SND_CLOCK .ds 1
JOYPAD1 .ds 1
JOYPAD2 .ds 1
; UNROM
    .org 0x8000
UNROM .ds 1
; CNROM
    .org 0x8000
CNROM .ds 1
; MMC1
    .org 0x8000
MMC1_CTRL .ds 1
    .org 0xA000
MMC1_VROM_LOW .ds 1
    .org 0xC000
MMC1_VROM_HIGH .ds 1
    .org 0xE000
MMC1_PRG .ds 1
; MMC3
    .org 0x8000
MMC3_CMD .ds 1
MMC3_PAGE .ds 1
    .org 0xA000
MMC3_MIRR .ds 1
MMC3_SRAM .ds 1
    .org 0xC000
MMC3_CLOCK .ds 1
MMC3_CLOCK_LATCH .ds 1
    .org 0xE000
MMC3_CLOCK_OFF .ds 1
MMC3_CLOCK_ON .ds 1
</pre>

Latest revision as of 23:23, 22 May 2022

Registers provide internal state storage for a device.

These may store a number, like the accumulator register in the CPU, or they may store other behaviour states, like the colour output of the PPU. The various cartridge mappers have registers that control banking, as well as other devices (e.g. IRQ timer).

A register might be entirely internal, or it might have a memory mapped address to provide external access via the CPU. Such registers are often referred to by this write address.

See: