NES 2.0 Mapper 558: Difference between revisions

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(The 93C66 EEPROM can operate with 8 or 16 bits word size.)
 
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* ''口袋妖怪꞉ 鑽石版'' (Pokémon: Diamond Edition, ES-1090)
* ''口袋妖怪꞉ 鑽石版'' (Pokémon: Diamond Edition, ES-1090)
* ''口袋精靈: 紅'' and its title screen hack ''宠物: 红'' (Pokémon: Red Edition, ES-1088)
* ''口袋精靈: 紅'' and its title screen hack ''宠物: 红'' (Pokémon: Red Edition, ES-1088)
* ''富甲三国'' (Fùjiǎ Sānguó)
* ''数码暴龙 4: 水晶版'' and its title screen hack '' 数码宝贝'' (Digimon 4: Crystal Edition)
* ''数码暴龙 4: 水晶版'' and its title screen hack '' 数码宝贝'' (Digimon 4: Crystal Edition)
* ''盟军敢死队 - Commandos''
* ''盟军敢死队 - Commandos''
The Yànchéng save the game state to a 93C66 512-byte serial EEPROM, while the Wàixīng games save to 8 KiB battery-backed WRAM. The NES 2.0 Header's PRG-NVRAM field distinguishes between the two board variants.
The Yànchéng games save the game state to a 93C66 512-byte serial EEPROM, its "ORG" pin tied to GND, selecting a word size of 8 bits. The Wàixīng games save to 8 KiB battery-backed WRAM. The NES 2.0 Header's PRG-NVRAM field distinguishes between the two board variants.


=Banks=
=Banks=
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         ++++- PRG A18..A15
         ++++- PRG A18..A15
    
    
* Note that if $5300.0 is 1, the two lowest bits are swapped during writing.
* Note that if $5300.0 is 0, the two lowest bits are swapped during writing.
* Changing the value of $5300.0 without writing to $5000 afterwards does not change the latched bits.
==PRG-ROM Bank High ($5100, write)==
==PRG-ROM Bank High ($5100, write)==
  Mask: $FB00
  Mask: $FB00
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   .... ..PP
   .... ..PP
           ++- PRG A20..A19
           ++- PRG A20..A19
* Note that if $5300.0 is 1, the two lowest bits are swapped during writing.
* Note that if $5300.0 is 0, the two lowest bits are swapped during writing.
* Games with 1 MiB PRG-ROM that set $5300.0=1 still use bit 0 to denote PRG A19; they must connect both ASIC PRG A19 and A20 outputs to the ROM chip's A19 pin.
==Microwire Interface ($5200, write)==
==Microwire Interface ($5200, write)==
  Mask: $FF00
  Mask: $FF00
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  D~7654 3210
  D~7654 3210
   ---------
   ---------
   .... .SCD
   .... .SDC
         ||+- 93C66 EEPROM DAT ($5300.0=0)/CLK($5300.0=1) output
         ||+- 93C66 EEPROM CLK ($5300.0=0)/DAT ($5300.0=1) output
         |+-- 93C66 EEPROM CLK ($5300.0=0)/DAT($5300.0=1) output
         |+-- 93C66 EEPROM DAT ($5300.0=0)/CLK ($5300.0=1) output
         +--- 93C66 EEPROM CS output
         +--- 93C66 EEPROM CS output


Note that if $5300.0 is 1, there are ''two'' effects on this register:
* the two lowest bits are swapped ''during writing'' before being latched;
* the two latched bits are swapped before being output ''as long as'' $5300.0 remains 1.
These two effects ''counteract'' each other, so that register $5200 effectively operates ''identically'' regardless of the $5300.0 value. When writing to $5300 and changing its bit 0 ''without'' writing to $5200 afterwards, ...
* the latched values of B and C remain as when they were written, but
* the choice of which latched bit to be output to the DAT and CLK pins changes;
or in other words, the DAT and CLK pins swap their values until $5200 is written to again.
==Mode ($5300, write)==
==Mode ($5300, write)==
  Mask: $FF00
  Mask: $FF00
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  D~7654 3210
  D~7654 3210
   ---------
   ---------
   .... .A?B
   .... .AB.
         | +- 0: Leave D0,D1 unmodified on register writes to $5000-$5200.
         |+- 0: Swap D0,D1 on all register writes to $5000-$5200.
         |    1: Swap D0,D1 on all register writes to $5000-$5200.
         |    1: Leave D0,D1 unmodified on register writes to $5000-$5200.
         +--- 0: PRG A15/A16=1
         +--- 0: PRG A15/A16=1
               1: PRG A15/A16 from $5000
               1: PRG A15/A16 from $5000
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* Writes to this register are ''not'' subject to D0/D1 bit-swapping, i.e. the register is not affected by its own bit 0.
* Writes to this register are ''not'' subject to D0/D1 bit-swapping, i.e. the register is not affected by its own bit 0.
* Because this register is initialized to $00 on reset, thus clearing bit 2 which causes PRG A15/A16 to be held high, the game will boot in 32 KiB PRG-ROM bank #3.
* Because this register is initialized to $00 on reset, thus clearing bit 2 which causes PRG A15/A16 to be held high, the game will boot in 32 KiB PRG-ROM bank #3.
* Changing the value of $5300.0 without writing to $5000-$5200 afterwards does not change the latched bits.
==Microwire Interface ($5500, read)==
==Microwire Interface ($5500, read)==
  Mask: $FF00
  Mask: $FF00
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Unlike [[INES Mapper 164]], the EEPROM input is ''not'' inverted.
Unlike [[INES Mapper 164]], the EEPROM input is ''not'' inverted.
=Notes=
=Notes=
* Setting $5300.0=1 will effectively swap PRG A15/A16 and PRG A19/A20. Cartridges using this mapper must be dumped with $5300=$04 during dumping, even if the games run with $5300=$07. Otherwise, PRG A15/A16 and PRG A19/A20 would be swapped both during dumping and emulation, negating the effect; such images will therefore not work with an accurate emulation of this mapper.
* CPU D0 and D1 are connected in reverse to the mapper blob compared to other circuit boards using this ASIC. This means that setting $5300.0 to 0, not to 1, will effectively swap PRG A15/A16 and PRG A19/A20. Cartridges using this mapper must be dumped with $5300=$07 during dumping to obtain a readout that matches that of a desoldered ROM chip.
=Note=
* The Wàixīng games using this mapper were previously set to 162/163 or 164, resulting in incompatibility either because of the different address of the PRG-ROM Bank High register (mapper 162/163) or the different startup bank (164).
The Wàixīng games using this mapper were previously set to 162/163 or 164, resulting in incompatibility either because of the different address of the PRG-ROM Bank High register (mapper 162/163) or the different startup bank (164).
=See also=
=See also=
* [[INES Mapper 162]]/163 swap the meaning of registers $5100 and $5200, and use the microwire interface only for protection purposes.
* [[INES Mapper 162]]/163 swap the effective meaning of registers $5100 and $5200, the meaning of the D0/D1 bit swap, and use the microwire interface only for protection purposes.
* [[INES Mapper 164]] is an earlier implementation without D0/D1 swapping, optional UNROM-like bankswitching, and a 1 bpp CHR mode.
* [[INES Mapper 164]] is an earlier implementation without D0/D1 swapping, optional UNROM-like bankswitching, and a 1 bpp CHR mode.
* [///forums.nesdev.org/viewtopic.php?f=9&t=20815 PCB images and analysis]

Latest revision as of 23:30, 19 February 2022

NES 2.0 Mapper 558 denotes the 燕城 (Yànchéng) YC-03-09 circuit board, used for the following games:

  • 口袋精靈: 水晶 (Pokémon: Crystal Edition)
  • 大話三國 (Dàhuà Sānguó)

A compatible circuit board with an unknown PCB code is used for the original editions of a few games from 外星 (Wàixīng):

  • Pet Family - 宠物大家族: 部落纷争 (ES-1081)
  • Pet Evolve - 宠物进化史 (ES-1085)
  • 口袋妖怪꞉ 鑽石版 (Pokémon: Diamond Edition, ES-1090)
  • 口袋精靈: 紅 and its title screen hack 宠物: 红 (Pokémon: Red Edition, ES-1088)
  • 数码暴龙 4: 水晶版 and its title screen hack 数码宝贝 (Digimon 4: Crystal Edition)
  • 盟军敢死队 - Commandos

The Yànchéng games save the game state to a 93C66 512-byte serial EEPROM, its "ORG" pin tied to GND, selecting a word size of 8 bits. The Wàixīng games save to 8 KiB battery-backed WRAM. The NES 2.0 Header's PRG-NVRAM field distinguishes between the two board variants.

Banks

  • CPU $6000-$7FFF: up to 8 KiB unbanked PRG-RAM, can be battery-backed
  • CPU $8000-$FFFF: 32 KiB switchable PRG-ROM bank
  • PPU $0000-$1FFF: 8 KiB unbanked CHR-RAM bank
  • Nametable mirroring: hard-wired

Registers

All registers are initialized to $00 on reset.

PRG-ROM Bank Low ($5000, write)

Mask: $FF00

D~7654 3210
  ---------
  .... PPPP
       ++++- PRG A18..A15
  • Note that if $5300.0 is 0, the two lowest bits are swapped during writing.

PRG-ROM Bank High ($5100, write)

Mask: $FB00

D~7654 3210
  ---------
  .... ..PP
         ++- PRG A20..A19
  • Note that if $5300.0 is 0, the two lowest bits are swapped during writing.

Microwire Interface ($5200, write)

Mask: $FF00

D~7654 3210
  ---------
  .... .SDC
        ||+- 93C66 EEPROM CLK ($5300.0=0)/DAT ($5300.0=1) output
        |+-- 93C66 EEPROM DAT ($5300.0=0)/CLK ($5300.0=1) output
        +--- 93C66 EEPROM CS output

Mode ($5300, write)

Mask: $FF00

D~7654 3210
  ---------
  .... .AB.
        |+-  0: Swap D0,D1 on all register writes to $5000-$5200.
        |    1: Leave D0,D1 unmodified on register writes to $5000-$5200.
        +--- 0: PRG A15/A16=1
             1: PRG A15/A16 from $5000
  • Writes to this register are not subject to D0/D1 bit-swapping, i.e. the register is not affected by its own bit 0.
  • Because this register is initialized to $00 on reset, thus clearing bit 2 which causes PRG A15/A16 to be held high, the game will boot in 32 KiB PRG-ROM bank #3.
  • Changing the value of $5300.0 without writing to $5000-$5200 afterwards does not change the latched bits.

Microwire Interface ($5500, read)

Mask: $FF00

D~7654 3210
  ---------
  .... .A..
        |
        |
        +--- 93C66 EEPROM DAT input

Unlike INES Mapper 164, the EEPROM input is not inverted.

Notes

  • CPU D0 and D1 are connected in reverse to the mapper blob compared to other circuit boards using this ASIC. This means that setting $5300.0 to 0, not to 1, will effectively swap PRG A15/A16 and PRG A19/A20. Cartridges using this mapper must be dumped with $5300=$07 during dumping to obtain a readout that matches that of a desoldered ROM chip.
  • The Wàixīng games using this mapper were previously set to 162/163 or 164, resulting in incompatibility either because of the different address of the PRG-ROM Bank High register (mapper 162/163) or the different startup bank (164).

See also

  • INES Mapper 162/163 swap the effective meaning of registers $5100 and $5200, the meaning of the D0/D1 bit swap, and use the microwire interface only for protection purposes.
  • INES Mapper 164 is an earlier implementation without D0/D1 swapping, optional UNROM-like bankswitching, and a 1 bpp CHR mode.
  • PCB images and analysis
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