INES Mapper 012: Difference between revisions

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(+FCEUX implementation differences and $4132 read reg)
 
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This mapper is an [[MMC3]] variant with a simple twist. Writing to $4020-5FFF will set an additional bit for each half of CHR to allow an extra 256K of ROM to be addressed. For example, the mapped page for the left half would be %Lxxxxxxxx where %xxxxxxxx is the result of the typical MMC3 logic.
{{DEFAULTSORT:012}}
[[Category:Mappers using $4020-$5FFF]][[Category:iNES Mappers]][[Category:MMC3-like mappers]]
'''iNES Mapper 012''' denotes ...
* the 哥德 (Gouder) '''SL-5020B''' circuit board ('''submapper 0''');
* ROM images that have been extracted from disk images for the Front Fareast Magic Card 4M [[RAM cartridge]] ('''submapper 1''').
Even as FFE 4M was assigned earlier (as "FFE F6xxx") than SL-5020B, the latter was emulated earlier and so is assigned submapper 0.


Otherwise all operations appear to be typical for MMC3A.
=SL-5020B (submapper 0)=
'''Submapper 0''''s circuit board mounts a chip-on-board variant of the same Huang-1 ASIC as mappers [[INES Mapper 014|14]], [[INES Mapper 116|116]] and [[INES Mapper 238|238]] plus GAL16V8 programmable logic. It is used for two games:
* Rex Soft's ''Dragon Ball Z 5'' cartrige;
* Version 7.5 of the homebrew hack ''Ultimate Mortal Kombat III''.
The Huang-1 ASIC functions exclusively as an MMC3A clone on this PCB; [[MMC3#IRQ_Specifics|MMC3A-specific IRQ behavior]] is necessary for running ''Dragon Ball Z 5''. The GAL16V8 provides an outer CHR bank register at $4132 to support 512 KiB of CHR-ROM:
Mask: $E100
D~7654 3210 (write)
  ---------
  ...B ...A
      |    +- CHR A18 when PPU A12=0
      +------ CHR A18 when PPU A12=1


Maybe the only game that uses this mapper is ''Dragon Ball Z 5''. It depends on this mapper operating as MMC3A variant. Choosing otherwise will result in the game hanging at boot-up as it gets stuck in an infinite loop with the IRQ reload set to 0 and continually getting re-triggered.
Because this register is implemented outside the ASIC, it is not affected by MMC3 $8000 bit 7, and writes take effect immediately. FCEUX instead emulates it as a temporary latch register that takes effect on the next write to an MMC3 CHR bank register. The homebrew hack ''Ultimate Mortal Kombat III'' relies on FCEUX' behavior and would therefore not work on the original PCB.


  Write Registers:
''Dragon Ball Z 5'' reads the same address to select between Chinese and English text.
  ---------------------------
Mask: $E100
 
  Range:  $4020-5FFF
D~7654 3210 (read)
 
  ---------
  $4020:  [...R ...L]
  .... ...A
    L = 256K CHR block for left (low) half of CHR (<$1000)
          +- Language-determining bit value
    R = 256K CHR block for right (high) half of CHR (>=$1000)


Note1: FCEUX instead uses the range $4100-$5FFF. DBZ5 itself seems to always write to $4132.
It was previously thought that the value of this bit reflects a jumper or solder pad. Pictures of the circuit board however show no sign of either. Either such a solder pad is hidden underneath the GAL16V8, or the GAL16V8 has the value hard-wired (to Chinese text in all known copies).


If the CHR ROM is 256K or smaller, CHR A18 isn't connected to anything, and thus this behaves as an ordinary MMC3A.
See also: [//forums.nesdev.org/viewtopic.php?p=160268#p160268 Forum thread about adding parts to an MMC3A board to make this mapper]
 
<gallery>
Note2: The above explanation is not what FCEUX does. Instead, it treats this register as an intermediate latch (just like register $5130 in MMC5). When game writes to CHR registers via $8001, bit from above register is used as additional CHR bank bit:
File:SL-5020B-front.jpg|PCB front
 
File:SL-5020B-back.jpg|PCB back
When $8000.7 = 0: L is used for CHR0 and CHR1 and R is used for CHR2, CHR3, CHR4, CHR5, CHR6
</gallery>
 
When $8000.7 = 1: R is used for CHR0 and CHR1 and L is used for CHR2, CHR3, CHR4, CHR5, CHR6
 
For Dragon Ball Z5 it does not matter, because it does change $4020 between writes to CHR regs. But there exists another game (''Ultimate Mortal Kombat III (Pit v+1 + Fat v+2) v7.5'') that change $4020 between writes to CHR registers. This game works correctly in FCEUX but does not in other emulators (like BizHawk). The difference in implementation of those mappers can be seen when selecting a middle fighter character from the bottom row - the sprites for one of the fighters will not be displayed properly.
 
Which implementation reflcts how real hardware works is unknown. Though, DBZ5 is a cartridge game that uses PCB with that mapper, while UMK3 v7.5 is one of homebrew hacks that just was ported from MMC3 to mapper 12 to get more CHR rom banks (latter versions switched to MMC5)
 
 
  Read Registers:
  ---------------------------
 
  Range:   $4020-5FFF
 
  $4020:  [.... ...D]
    D = value of PCB jumper (0 = English version of game, 1 = Chinese version of game)


Note: FCEUX uses the range $4100-$5FFF. DBZ5 itself seems to always read from $4132.
=Front Fareast Magic Card 4M (submapper 1)=
There exist different ROM of the game ('''Dragon Ball Z 5 - Dragon Ball Z Super (Unl) (Ch) [!]''), which has the the routine that reads above register replaced with a menu.
'''Submapper 1''' denotes ROM images that have been extracted from disk images for the ''Front Fareast Magic Card 4M'' [[RAM cartridge]]. It represents games whose [[Game_Doctor/Magic_Card_FDS_Format#Front_Fareast_Magic_Card_1M.2F2M.2F4M_disks|Doctor Header file]] denotes a Magic Card 4M disk (byte $0 bit 7 set, bits 4 or 5 set, byte $7=$00). Refer to the [[Super Magic Card]] article for details on bankswitching. The Super Magic Card's registers are initialized to:
; Play mode, WRAM bank 0, 1 KiB CHR mode disabled
[[Super_Magic_Card#Super_Magic_Card_mode_.28.244500.2C_write-only.29|$4500]] = $42
; PRG memory write-protected, two-screen mirroring
[[Super_Magic_Card#1M_banking_mode_.28.2442FC-.2442FF.2C_write-only.29|$42FF]] = $20 | (verticalMirroring? 0x00: 0x10)
; 4M banking mode enabled
[[Super_Magic_Card#2M.2F4M_PRG_banking_mode_.28.2443FC-.2443FF.2C_write-only.29|$43FC]] = $00
; Initial PRG register content
$4504 = Number of 8 KiB PRG banks -4
$4505 = Number of 8 KiB PRG banks -3
$4506 = Number of 8 KiB PRG banks -2
$4507 = Number of 8 KiB PRG banks -1


The [[iNES]] header may specify a [[INES#Trainer|512-byte trainer]] (corresponding to [[Game_Doctor/Magic_Card_FDS_Format#Front_Fareast_Magic_Card_1M.2F2M.2F4M_disks|Doctor Header file]]'s byte $0 bit 6 being set), which must be loaded to $7000-$71FF, be writable, and (on a hard reset) initialized by JSRing to $7003 before JMPing to the game's reset vector.


Mapper 12 is also used for FFE disk images. See [[INES Mapper 006|Mapper 6]] for some additional details. (FIXME: does the FFE usage comply with the above info, or is there a conflict between different mapper 12 definitions?)
Battery-saving of WRAM content is not supported by any Magic Card model. Hard-resetting a game while restoring previously-saved WRAM content in emulators interferes with the correct operation of the trainer's program.


See also: [//forums.nesdev.org/viewtopic.php?p=160268#p160268 Forum thread about adding parts to an MMC3A board to make this mapper]
Because the Magic Card 4M only had 32 KiB of CHR-RAM, CHR data is loaded into ''PRG'' address space at offset $40000, i.e. the second half of its 512 KiB of PRG memory, so that the trainer program can copy portions of it to 32 KiB CHR-RAM as needed. The iNES header specifies it as CHR-ROM nonetheless so that the initial PRG registers can be correctly initialized to point to the game's reset vector.
 
{{DEFAULTSORT:012}}
[[Category:Mappers using $4020-$5FFF]][[Category:iNES Mappers]][[Category:MMC3-like mappers]]

Latest revision as of 00:15, 11 December 2021

iNES Mapper 012 denotes ...

  • the 哥德 (Gouder) SL-5020B circuit board (submapper 0);
  • ROM images that have been extracted from disk images for the Front Fareast Magic Card 4M RAM cartridge (submapper 1).

Even as FFE 4M was assigned earlier (as "FFE F6xxx") than SL-5020B, the latter was emulated earlier and so is assigned submapper 0.

SL-5020B (submapper 0)

Submapper 0's circuit board mounts a chip-on-board variant of the same Huang-1 ASIC as mappers 14, 116 and 238 plus GAL16V8 programmable logic. It is used for two games:

  • Rex Soft's Dragon Ball Z 5 cartrige;
  • Version 7.5 of the homebrew hack Ultimate Mortal Kombat III.

The Huang-1 ASIC functions exclusively as an MMC3A clone on this PCB; MMC3A-specific IRQ behavior is necessary for running Dragon Ball Z 5. The GAL16V8 provides an outer CHR bank register at $4132 to support 512 KiB of CHR-ROM:

Mask: $E100

D~7654 3210 (write)
  ---------
  ...B ...A
     |    +- CHR A18 when PPU A12=0
     +------ CHR A18 when PPU A12=1

Because this register is implemented outside the ASIC, it is not affected by MMC3 $8000 bit 7, and writes take effect immediately. FCEUX instead emulates it as a temporary latch register that takes effect on the next write to an MMC3 CHR bank register. The homebrew hack Ultimate Mortal Kombat III relies on FCEUX' behavior and would therefore not work on the original PCB.

Dragon Ball Z 5 reads the same address to select between Chinese and English text.

Mask: $E100

D~7654 3210 (read)
  ---------
  .... ...A
          +- Language-determining bit value

It was previously thought that the value of this bit reflects a jumper or solder pad. Pictures of the circuit board however show no sign of either. Either such a solder pad is hidden underneath the GAL16V8, or the GAL16V8 has the value hard-wired (to Chinese text in all known copies).

See also: Forum thread about adding parts to an MMC3A board to make this mapper

Front Fareast Magic Card 4M (submapper 1)

Submapper 1 denotes ROM images that have been extracted from disk images for the Front Fareast Magic Card 4M RAM cartridge. It represents games whose Doctor Header file denotes a Magic Card 4M disk (byte $0 bit 7 set, bits 4 or 5 set, byte $7=$00). Refer to the Super Magic Card article for details on bankswitching. The Super Magic Card's registers are initialized to:

; Play mode, WRAM bank 0, 1 KiB CHR mode disabled
$4500 = $42 

; PRG memory write-protected, two-screen mirroring
$42FF = $20 | (verticalMirroring? 0x00: 0x10)

; 4M banking mode enabled
$43FC = $00

; Initial PRG register content
$4504 = Number of 8 KiB PRG banks -4
$4505 = Number of 8 KiB PRG banks -3
$4506 = Number of 8 KiB PRG banks -2
$4507 = Number of 8 KiB PRG banks -1

The iNES header may specify a 512-byte trainer (corresponding to Doctor Header file's byte $0 bit 6 being set), which must be loaded to $7000-$71FF, be writable, and (on a hard reset) initialized by JSRing to $7003 before JMPing to the game's reset vector.

Battery-saving of WRAM content is not supported by any Magic Card model. Hard-resetting a game while restoring previously-saved WRAM content in emulators interferes with the correct operation of the trainer's program.

Because the Magic Card 4M only had 32 KiB of CHR-RAM, CHR data is loaded into PRG address space at offset $40000, i.e. the second half of its 512 KiB of PRG memory, so that the trainer program can copy portions of it to 32 KiB CHR-RAM as needed. The iNES header specifies it as CHR-ROM nonetheless so that the initial PRG registers can be correctly initialized to point to the game's reset vector.